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北京时间·🕒 发布 03-12 06:00:39时区推断·⟳ 抓取 06-12 02:26:23回填·⚡ 决策 06-18 01:13:04·131.8 天前
Marvell 在 DesignCon 2026 发布 PCIe 8.0 SerDes 并联合 TE Connectivity 展示 AI 互连 demo
📄 原文Marvell Technology↗ 原文
At DesignCon 2026, Marvell introduced PCIe 8.0 SerDes delivering up to one terabyte per second of bidirectional bandwid…
日 K 取自复盘打分切片 · 蓝点/蓝虚线 = 纸面入场价 · 灰虚线 = 纸面离场 · 持有期红底 = 赚(价格在入场线上方)、绿底 = 亏
怎么买 限价买入 不高于昨收 +4%、2 个交易日内有效
怎么卖 止盈 +5%(半仓)/+10%(清仓) · 止损 -5% · 时间止损 5日
失效/反转 竞品同期发布更优 PCIe 8.0 方案或客户验证未达预期
日 K 取自复盘打分切片 · 蓝点/蓝虚线 = 纸面入场价 · 灰虚线 = 纸面离场 · 持有期红底 = 赚(价格在入场线上方)、绿底 = 亏
怎么买 限价买入 不高于昨收 +2%、2 个交易日内有效
怎么卖 止盈 +3%(半仓)/+6%(清仓) · 止损 -3% · 时间止损 3日
失效/反转 Marvell 澄清 TE 仅为普通线材供应商而非核心联合研发
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原文全文
展开原文 · 746 字
At DesignCon 2026, Marvell introduced PCIe 8.0 SerDes delivering up to one terabyte per second of bidirectional bandwidth for next‑generation AI interconnects.
In this video, Desh Mirle Jayaprakash highlights a demo with TE Connectivity that showcases ultra‑low jitter, robust equalization and best‑in‑class bit error performance under real system conditions. The demonstration enables customers and ecosystem partners to begin pathfinding new architectures for fastest CPU to CPU communication, GPU to GPU communication and high‑bandwidth links across CPUs, GPUs, NICs and DPUs.
As AI servers and systems scale to hundreds of accelerators, PCI becomes the backbone of communication, and Marvell is leading the industry toward the PCIe 8 era.
In this video, Desh Mirle Jayaprakash highlights a demo with TE Connectivity that showcases ultra‑low jitter, robust equalization and best‑in‑class bit error performance under real system conditions. The demonstration enables customers and ecosystem partners to begin pathfinding new architectures for fastest CPU to CPU communication, GPU to GPU communication and high‑bandwidth links across CPUs, GPUs, NICs and DPUs.
As AI servers and systems scale to hundreds of accelerators, PCI becomes the backbone of communication, and Marvell is leading the industry toward the PCIe 8 era.
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