三星平泽P5启动混合键合量产线建设并评估Besi及韩国设备供应商

Samsung Electronics Begins Construction of Hybrid Bonding Mass-Production Line at Pyeongtaek P5

Samsung Electronics has begun constructing a die-to-wafer (D2W) hybrid bonding mass-production line at its Pyeongtaek Campus. The line will be used to manufacture next-generation high-bandwidth memory (HBM) and logic semiconductors.

According to semiconductor industry sources on the 21st, Samsung Electronics has selected Dutch semiconductor back-end equipment maker BE Semiconductor Industries (Besi) as its preferred supplier and initiated the process of acquiring 50 D2W hybrid bonding machines. The equipment is slated for installation at the P5 fab on its Pyeongtaek Campus.

During Besi’s first-quarter earnings conference call in April, CEO Richard Blickman said, “We expect to see something more definitive regarding Samsung Electronics’ adoption of hybrid bonders around the middle of this year.” At the time, Besi’s hybrid bonders were undergoing Samsung’s qualification testing.

However, it will take more time to finalize the order. Samsung has requested modifications to the equipment architecture, making it difficult to determine a specific delivery date. Such modifications involve changing certain specifications—such as the design, components, or modules—to meet a customer’s requirements. The fact that Besi’s hybrid bonders cost approximately KRW 6 billion (about $4.3 million) each, roughly twice the price of competing products, is also said to be prolonging negotiations.

“Besi supplies hybrid bonders to semiconductor companies worldwide, including TSMC and Micron, and is reluctant to modify the equipment architecture exclusively for Samsung,” an industry source said. “Samsung considers Besi’s equipment the best option, but because coordination has been difficult, it is also considering products from Korean equipment makers that can respond more quickly and flexibly.”

SEMES, Samsung Electronics’ semiconductor equipment subsidiary, has also received a request to supply D2W hybrid bonders for the mass-production line. The company hopes to secure orders for two hybrid bonding production lines at the Pyeongtaek Campus.

“SEMES felt a strong sense of crisis when Samsung initially selected Besi’s equipment, but the situation has recently begun to change,” another industry source said.

SEMES completed development of its D2W hybrid bonder early this year and supplied a unit to Samsung Electronics for performance qualification. This suggests that the equipment has passed the testing process.

Samsung is also considering Hanwha Semitech as a hybrid bonder supplier. In February, Hanwha Semitech completed development of its second-generation D2W hybrid bonder, the “SHB2 Nano.” It subsequently supplied an evaluation unit to SK hynix in April.

The equipment was delivered as an integrated cluster system combining the bonder with a wafer-handling equipment front-end module (EFEM) from Cymechs, a plasma activation module from Hanwha Semitech, and a cleaning module from ZEUS.

Samsung’s construction of a D2W hybrid bonding mass-production line at its Pyeongtaek Campus is related to the packaging processes for HBM and logic semiconductors. According to industry sources, Samsung has pursued a hybrid bonding line for next-generation HBM at its Pyeongtaek Campus in addition to its Cheonan Campus, which serves as a major semiconductor back-end packaging hub.

Using hybrid copper bonding (HCB), rather than conventional thermocompression (TC) bonding, to stack HBM core dies (DRAM chips) can significantly improve performance, power consumption, and thermal characteristics. This is because the technology directly bonds copper and dielectric materials without using metal protrusions known as micro-bumps, thereby shortening the interconnect length between devices.

The technology is particularly likely to be used for customer-specific, or custom, HBM (cHBM). In cHBM, Samsung replaces the conventional base die with a logic die incorporating the customer’s computing circuitry and intellectual property (IP). This logic die assists external central processing units (CPUs) and graphics processing units (GPUs) with computation while optimizing data transmission.

Samsung plans to implement a three-dimensional system-in-package (3D SiP) architecture in which HBM DRAM layers are stacked vertically and directly on top of the logic die.

Samsung Electronics’ foundry business also unveiled “3D Cube-H,” a next-generation 3D vertical stacking solution based on hybrid bonding, last month. Designed for next-generation artificial intelligence chips and high-performance computing (HPC) systems, the heterogeneous integration packaging technology offers improved performance, power efficiency, and bandwidth compared with conventional packaging technologies. Samsung Foundry is currently actively proposing the solution to customers for adoption.

Hybrid bonders from the equipment suppliers are expected to begin arriving and being installed at the Pyeongtaek Campus toward the end of this year. However, Samsung internally expects large-scale production using hybrid bonding to become feasible around 2030, as the technology is considerably more challenging than TC bonding.

“We expect hybrid bonding to enter full-scale use around 2029, when Nvidia’s next-generation AI accelerator, Feynman, is expected to arrive,” a third industry source said.