长鑫存储（CXMT）成功将High-k金属栅（HKMG）工艺导入G4制程DRAM量产，TechInsights确认其技术追赶进展

China’s CXMT Successfully Applies High-k Materials to DRAM Mass Production, Closing In on Samsung and SK hynix

China’s ChangXin Memory Technologies (CXMT), a late entrant to the DRAM industry, is rapidly narrowing the technology gap with market leaders. The company has reportedly succeeded in applying high-k dielectric materials—once considered largely the domain of leading memory manufacturers—to its latest DRAM products in mass production.

In response, Samsung Electronics and SK hynix are accelerating development of next-generation architectures such as 4F² and 3D DRAM in an effort to maintain their technological lead.

Jeongdong Choi, Senior Vice President at TechInsights, discussed the latest roadmap for advanced DRAM technology development during a memory industry trends webinar on the 27th. TechInsights is a semiconductor-focused research and analysis firm.

China Begins Full-Scale Adoption of High-Performance High-k Materials, Rapidly Catching Up With Industry Leaders

The global DRAM market has traditionally been dominated by the “Big Three”: South Korea’s Samsung Electronics and SK hynix, and U.S.-based Micron. These companies have been expanding shipments of high-value AI memory products through the commercialization of 12nm-class DRAM and high-bandwidth memory (HBM).

Chinese companies, however, are catching up quickly. CXMT, currently China’s largest DRAM manufacturer, has successfully commercialized DDR5 and LPDDR5 products based on its G4, or 16nm-class, process.

More recently, CXMT has also begun using advanced materials in DRAM transistors that had previously been employed primarily by leading memory manufacturers.

“The important point is that our analysis shows CXMT has successfully introduced high-k metal gate, or HKMG, technology into its G4 process and LPDDR5X products,” Choi said.

High-k materials are used in insulating layers that prevent leakage current between circuits. Because they can store more charge at the same voltage, they enable more aggressive device scaling than conventional silicon dioxide (SiO₂) gate dielectrics. Samsung Electronics, SK hynix, and Micron began adopting these materials around four to five years ago.

CXMT is also advancing its HBM technology. The company is reportedly in the risk-production stage for HBM2E, the third generation of HBM, using its G3, or 18nm-class, DRAM process. It is also sampling HBM3 based on its G4 process.

“CXMT remains roughly two generations behind the leading players, but it continues to advance its HBM roadmap toward higher-performance memory solutions,” Choi said. “Its G5, or 15nm-class, DRAM process is also under development.”

DRAM Big Three Pursue Technological Shift Toward 4F² and 3D DRAM

Samsung Electronics, SK hynix, and Micron are seeking to maintain their technological advantage by developing next-next-generation DRAM below the 10nm node, known as D0a. In particular, 4F² and 3D DRAM, which fundamentally alter the conventional DRAM cell structure, are emerging as the most likely candidates.

“Based on our current assessment, Samsung Electronics and SK hynix are more likely to pursue 4F² DRAM,” Choi said. “Micron, on the other hand, appears more likely to move directly to 3D DRAM.”

4F² DRAM is a next-generation architecture that changes the orientation of the memory cell—the smallest unit used to store data—from a conventional planar arrangement to a vertical structure.

The “F²” notation refers to the area occupied by a memory cell relative to the minimum feature size, or F, of the manufacturing process.

Conventional DRAM typically uses a 6F² cell architecture. Reducing the cell area increases DRAM density, which can improve data-processing capability and power efficiency. This is why the industry is increasingly focused on 4F² structures.

3D DRAM, meanwhile, vertically arranges cells that have traditionally been integrated horizontally by standing up either the bitlines or wordlines. Bitlines and wordlines are the interconnect structures used to operate the transistors within each memory cell.

With a 3D DRAM architecture, more cells can be packed into the same footprint while increasing spacing between transistors, which can also reduce interference.

However, 3D DRAM is considered significantly more technically challenging than 4F² because it requires the introduction of new materials, bonding technologies, and other complex process innovations.

“3D DRAM remains an extremely challenging technology and would introduce substantial process complexity and yield issues if commercialized at the D0a generation,” Choi said. “For this reason, 4F² DRAM is emerging as the more practical candidate for the D0a generation.”