Jukan转述韩媒/设备业高管口径称长鑫存储HBM3 8-Hi试产良率仅约25%~30%、TSV工艺不成熟，四个里有三个不良

"Three out of four are defective"... China's CXMT struggles with HBM yields, with immature TSV technology to blame

ChangXin Memory Technologies (CXMT), China's largest DRAM maker, has begun trial production of fourth generation high bandwidth memory (HBM3), but initial yields are barely improving. Yields are reported to have stalled at 25%, roughly one third of the so called "golden yield" of 80% that the semiconductor industry treats as the threshold for volume production. The gap is stark compared with SK hynix, which has been mass producing the same product since 2022 and has secured yields above 90%. Industry sources point to the gap in maturity of through-silicon via (TSV) technology, the core process for stacking and connecting multiple DRAM layers, as the root cause.

◇ "DRAM has caught up, but HBM stacking is a different problem"

According to a senior official at a semiconductor equipment company familiar with CXMT's situation on the 9th, the yield of CXMT's HBM3 8-High product is stuck at around 30% in the front end process. Of the products that survive that stage, only about 70% are recognized as final good units after passing through the back end process. In simple terms, if 100 HBM3 units are started, close to 80 of them fail the final test.

CXMT is reported to be supplying the small volumes of HBM samples it produces this way to Chinese companies such as Alibaba's T-Head and Cambricon while continuing its yield improvement work. The problem is that the issue does not lie in the fine process technology of the DRAM itself. A semiconductor equipment industry official explained, "There is no major problem with the standard DRAM that CXMT makes on its 'G4' (17nm class) process used for HBM. However, the DRAM dies used for HBM are larger in area than standard products and have more demanding electrical specifications, so even on the same process they are much harder to pass the acceptance criteria."

In other words, CXMT's fundamental capability in making standard DRAM has risen to a considerable level, but a bottleneck is emerging at the stage of converting it into the high performance product that is HBM. At the heart of that bottleneck, according to industry sources, is the TSV process.

◇ The real hurdle is TSV... "Impossible to catch up without years of accumulated know how"

TSV stands for "Through Silicon Via" and refers to the microscopic copper wiring that passes vertically through each layer to carry electrical signals when DRAM is stacked in multiple layers, as in HBM. It is a highly demanding process in which a DRAM wafer is thinned down to several tens of micrometers, a fraction of the thickness of a human hair, after which thousands of tiny holes are drilled through that thin silicon plate and filled completely with copper. A single hole that is misaligned or not properly filled can cause the entire layer to be rejected, making it one of the semiconductor processes with the most stringent precision requirements.

The consensus in the industry is that this is the process where the technology gap between CXMT and the leading companies is widest. According to analysis by semiconductor research firm Nomad Semi, Samsung Electronics' HBM2 (second generation HBM) has more than 5,000 TSVs per die and SK hynix's HBM3 has more than 8,000, while CXMT's is understood to have only around 3,000. A smaller number of TSVs means sacrificing bandwidth (data processing speed) in exchange for lower process difficulty, yet even so CXMT's yields still fall far short of Samsung and SK hynix. TSV is a process that is challenging even for the industry leader: SK hynix itself publicly disclosed in 2024 that the yield of the standalone TSV process was only 40 to 60% at the time.

On top of this, yield losses also occur in the back end (stacking and bonding) stage where the dies are actually stacked and joined. If even one of the eight dies is misaligned, if a microscopic void forms at a bonding interface, or if a layer warps during the thermocompression bonding process (warpage), the entire stack is scrapped. Because the number of possible failure points grows with each additional layer, the difficulty rises exponentially. Given that CXMT is already showing such poor yields at 8-High, some expect it to face even greater difficulties when moving to higher stacks such as 12-High.

A semiconductor industry official explained, "The TSV process is an area that only stabilizes after years of accumulated wafer handling know how. Chinese companies have rapidly closed the gap in the fine process technology of DRAM itself, but back end know how such as TSV and bonding is difficult to catch up on in a short period." He added, "That said, Samsung Electronics also had initial HBM4 (sixth generation HBM) production yields below 60% in February this year and raised them to 80% within six months, so it is too early to declare CXMT's 25% yield a 'failure.'"