英伟达发布Spectrum-X Ethernet技术博客，强化AI工厂网络架构叙事但无新增商业订单

The massive growth of generative AI has fundamentally altered data center design. As distributed model training scales to span hundreds of thousands of GPUs, the scale-out network connecting these nodes has emerged as a first-order performance bottleneck.
For decades, traditional off-the-shelf Ethernet has been the undisputed king of enterprise and cloud networking. It is cheap, standardized, and highly effective at handling general-purpose, high-entropy web traffic. However, when traditional Ethernet is forced to handle the massive, highly synchronized communication patterns required by AI architectures, it hits a physical wall.
To bridge this gap, NVIDIA introduced Spectrum-X Ethernet, a hardware-accelerated networking architecture designed from the ground up for giga-scale AI factories. Unlike traditional Ethernet, which relies on decades-old routing and congestion control paradigms, Spectrum-X Ethernet co-designs high-performance switches and host-side network interface cards (NICs) to deliver predictable low latency, high fabric utilization, and robust resilience under extreme load and stress.
This post explores the structural limitations that make traditional Ethernet ill-suited for AI workloads, deconstructs the unique architectural principles of Spectrum-X Ethernet, and explains how Spectrum-X Multiplane technology maximizes bisection bandwidth and accelerates Time-to-AI.
Standard data center traffic is high entropy; millions of small, independent flows travel in different directions. Equal-Cost Multi-Path (ECMP) routing uses static flow hashing to spread them across parallel paths, generally producing balanced utilization.
AI training traffic is low entropy. GPUs continuously synchronize through collectives such as All-Reduce, All-Gather, and All-to-All, creating relatively few, very large, synchronized flows. This exposes three limitations of traditional Ethernet:
- Hash collisions and stragglers: ECMP doesn’t account for real-time congestion, so large flows may collide on one link while others are underused. Because synchronous collectives finish only when their slowest flow completes, one congested path can delay the collective and leave many GPUs idle.
- Lossy versus lossless operation: Congestion can overflow switch buffers and trigger packet loss and retransmission, delays that significantly hurt AI performance. RoCEv2 deployments often use Priority Flow Control (PFC) to reduce loss, but pause frames can propagate congestion, create head-of-line blocking, and potentially stall the fabric.
- Slow congestion control: Protocols such as Data Center Quantized Congestion Notification (DCQCN) can be difficult to tune for synchronized AI bursts. Delayed or excessive reactions can cause buffer buildup, underutilization, and latency spikes.
- Near-Perfect Multi-Tenant Isolation: With traditional Ethernet, “noisy neighbor” traffic from one job can bleed into another, causing an All-to-All collective’s bandwidth to collapse by more than 80%. This isolation failure was demonstrated in a DeepSeek-V3 LLM training simulation. When running standalone, standard Ethernet achieved a training step time of 735 ms. However, when background “noise” traffic was introduced, standard Ethernet’s step times inflated to 1.18 seconds (a 1.6x slowdown). Spectrum-X Ethernet, by isolating congestion per plane and dynamically routing around hotspots, maintained a stable training step time of 668 ms under both standalone and heavily congested multi-tenant conditions representing virtually zero degradation.
At 800 gigabits per second (Gbps) and beyond, propagation delay remains fixed by the speed of light, but the bandwidth-delay product is massive. To avoid queue build-up and packet loss, a network fabric must react to congestion in real-time, at microsecond timescales.
Because software-based control paths can’t react within these tight windows, Spectrum-X Ethernet implements full hardware acceleration as a core structural requirement. The fundamental design principle of Spectrum-X Ethernet is the separation of hardware-accelerated control loops by scope, signal, and responsibility. By decomposing network control into three distinct, non-interfering loops, Spectrum-X Ethernet resolves congestion at its natural timescale without creating feedback loops that destabilize the fabric.
Unlike traditional Ethernet’s static, hash-based ECMP routing, Spectrum-X Ethernet switches implement per-packet Adaptive Routing (AR). Utilizing a quantized hardware approximation of the Join-Shortest-Queue (JSQ) algorithm, the switch samples the queue depth of every egress port in an ECMP group at sub-microsecond intervals. When a packet arrives, the switch dynamically steers it to the least-congested physical port. This stateless, flow-agnostic mechanism reacts within hundreds of nanoseconds to transient local imbalances, keeping switch queues small and preventing localized hotspots.
While AR equalizes path utilization within the fabric, it can’t resolve endpoint incast, a scenario where multiple senders simultaneously transmit data to a single receiver, saturating the receiver’s egress port. To handle this, Spectrum-X Ethernet implements an advanced, hardware-accelerated Congestion Control (CC) mechanism.
Crucially, Spectrum-X Ethernet co-designs the switch and SuperNIC response: the switch only generates Explicit Congestion Notification (ECN) marks when its adaptive routing capacity is completely exhausted and the queue continues to grow. Senders utilize precise RTT probes combined with ECN marks to adjust their sending rates at RTT timescales. This prevents the network from overreacting to short-lived micro-bursts (which AR easily balances) while providing a rapid, precise rate reduction when genuine, endpoint-level congestion occurs.
Operating at the host edge, the Plane Load Balancer (PLB) is a dedicated hardware engine inside the Spectrum-X Ethernet SuperNIC (such as the NVIDIA ConnectX). The PLB dynamically distributes packets across multiple network planes, using a combination of local queue feedback and end-to-end, per-plane congestion telemetry. This mechanism is discussed in depth below.
To scale an AI factory to hundreds of thousands of GPUs, traditional networking architectures require adding additional tiers (e.g., moving from a 2-tier to a 3-tier fat-tree topology). However, adding tiers is highly problematic: it adds latency, increases jitter, introduces load imbalance, and massively inflates the cost of optics, cabling, and power.
To solve the scaling challenge, modern AI data centers leverage a Multiplane Topology. Instead of building a single, massive, multi-tiered network fabric, a Multiplane Topology decomposes a single host’s massive network bandwidth (for example, 800 Gbps from an 8-lane ConnectX SuperNIC) into multiple lower-speed, physically independent network planes (for example, four separate 200 Gbps planes). Each plane is built as a highly efficient, shallow two-tier fat tree.
To connect the hosts to these planes, passive optical devices such as shuffle-boxes or trunk cables are utilized at the host edge. These devices route fibers from each multi-port NIC to all independent planes, exposing massive path diversity at the host edge while maintaining complete NIC-to-NIC reachability. This allows a simple two-tier topology to scale to over 128,000 endpoints, or up to 16 million endpoints with a three-tier topology, without introducing the latency and jitter bottlenecks of a traditional multi-tier fabric topology.
While a Multiplane Topology offers massive theoretical bandwidth, it is only effective if traffic is perfectly balanced across all planes. Some standard architectures attempt to solve this by oblivious spraying, where packets are distributed sequentially across all planes at the transport layer without any visibility into individual plane conditions.
This approach breaks down completely in the real world. At giga-scale, physical faults, optical connector degradation, and fiber link flaps are steady-state operating realities. If a single fiber link in Plane 2 degrades or flaps, the capacity of that plane drops. Because oblivious spraying is blind to this asymmetry, it continues to dump equal amounts of traffic onto the degraded plane. As a result, the entire network’s performance is bottlenecked by the slowest, degraded plane, and a single localized link flap’s blast radius is amplified to encompass the entire multiplane cluster.
To unlock the true potential of multiplane architectures, Spectrum-X Multiplane technology implements a hardware-accelerated Plane Load Balancer (PLB) directly in the SuperNIC silicon. The Plane Load Balancer makes the multiplane architecture completely transparent to the application layer; the operating system and the collective communication libraries see only a single, unified RoCE device. All traffic distribution, load balancing, and failure failover are handled entirely within the Spectrum-X Ethernet hardware.
In concert with the Spectrum-X Ethernet switch, the PLB operates via a unique, stateful, two-stage hierarchical selection process for every packet transmitted:
- End-to-End Congestion Filtering: For every destination GPU, the SuperNIC maintains independent, stateful Congestion Control contexts; one for each physical plane. Each context independently monitors RTT probes and processes Congestion Notification Packets (CNPs) to calculate the real-time rate allowance of its specific plane. Before a packet is sent, the SuperNIC compares the required transmission rate against the allowance of each plane. Any plane experiencing end-to-end congestion or link failure is temporarily filtered out of the eligible set.
- Local Queue Selection: From the remaining, healthy, uncongested planes, the SuperNIC hardware selects the plane with the shallowest local egress queue. This mirrors the switches’ Adaptive Routing mechanism at the host edge.
By separating CC state per plane and combining it with local egress queue depth, Spectrum-X Ethernet isolates congestion to the affected plane. If Plane 2 experiences a link failure, the Connect-X SuperNIC immediately detects the RTT timeout, masks Plane 2 from the eligible set, and transparently redirects all traffic across the remaining three healthy planes in under 3 milliseconds thus preserving 75% of the total line-rate bisection bandwidth.
To validate these architectural designs, NVIDIA and researchers have rigorously evaluated Spectrum-X Ethernet on production-grade clusters and high-fidelity simulations. The results demonstrate a stark contrast between Spectrum-X Ethernet and traditional, off-the-shelf Ethernet under high utilization, failure scenarios, and multi-tenant environments:
- Multiplane resiliency: For example, when a localized 20% switch-to-switch connectivity failure occurs on just one plane of an 8-plane network, a traditional Ethernet multiplane network immediately bottlenecks. Because it relies on oblivious load balancing, its performance across every single plane collapses to match the degraded plane, limiting the entire fabric to 80% capacity. In contrast, Spectrum-X Multiplane uses its stateful PLB to dynamically route around the localized bottleneck, keeping the seven healthy planes running at 100% capacity while only the degraded plane operates at 80%. By utilizing all available healthy capacity rather than sinking to the lowest common denominator, Spectrum-X Multiplane delivers a 1.2x higher overall All-to-All collective bandwidth during failures, providing the graceful, capacity-proportional degradation necessary to keep massive AI training jobs moving.
- Predictable high-utilization performance: Under a worst-case RDMA bisection benchmark, traditional Ethernet’s static ECMP routing collapses due to flow-hash collisions, with some GPU pairs experiencing throughput drops down to 25 Gbps. Spectrum-X Ethernet, utilizing AR and PLB, delivers a tight, predictable bandwidth distribution, sustaining 98% of the theoretical line rate across all GPU pairs. Furthermore, while traditional Ethernet exhibits wide latency jitter with a 99th percentile (P99) tail latency reaching 22 µs, Spectrum-X Ethernet maintains a low, tightly clustered P99 tail latency of just 8 to 9 µs under 75% network load.
- Seamless failover resiliency: When a link on a host-to-leaf connection flaps, traditional Ethernet’s software-based or non-accelerated load balancers require upwards of 1.08 seconds to recover and reroute traffic. This causes massive communication stalls that freeze GPU collective operations. In contrast, Spectrum-X Ethernet’s hardware-accelerated PLB detects the failure and completes the failover in just 2.68 milliseconds. This is a 400x speedup that absorbs transient failures transparently without disrupting ongoing LLM training steps.
A final consideration is that link failures are inevitable, but their performance impact should remain proportional to the loss of physical connectivity. Achieving this is difficult because multiple faults along a path can severely degrade connectivity for many source-destination pairs.
Traditional Ethernet degrades non-proportionally under cable faults and link flaps; dropping 10% of leaf uplinks can cause collective bandwidth to collapse by 50% or more due to routing asymmetry. Spectrum-X Ethernet degrades strictly capacity-proportionally. Under a 10% fabric link failure scenario, Spectrum-X Ethernet maintains near-ideal performance, with bandwidth degrading by a proportional 11% and tail latency increasing by a mere 7%.
This robust resiliency ensures that operators can run training workloads at near-optimal efficiency even before all physical infrastructure issues are fully resolved, drastically reducing “Time-to-AI”.
The transition from general-purpose cloud computing to giga-scale generative AI represents a fundamental shift in networking requirements. Traditional off-the-shelf Ethernet, built on the assumptions of high-entropy traffic, static routing, and software-controlled congestion loops, is fundamentally incapable of meeting the microsecond-scale, zero-jitter demands of synchronous AI collectives.
Spectrum-X Ethernet rewrites the networking rulebook. By decoupling and hardware-accelerating the key control loops with adaptive routing within the fabric, targeted congestion control at the transport layer, and PLB at the host edge, Spectrum-X Ethernet delivers the predictable, stable, and ultra-low-latency performance that giga-scale AI demands. Additionally, Spectrum-X Multiplane technology provides a robust, highly resilient, and operationally visible network fabric that simplifies cluster scaling, protects multi-tenant workloads, and minimizes “Time-to-AI”. For any organization building an AI factory, Spectrum-X Ethernet is not just a performance optimization—it is an architectural necessity.
To learn more about Spectrum-X Ethernet and Spectrum-X Multiplane, read the published whitepaper here.
- Khashab, S., et al. (2025). “High-Speed Networking for Giga-Scale AI Factories.” NVIDIA Technical White Paper
- Bai, W., et al. (2023). “Empowering Azure Storage with RDMA.” Proceedings of the USENIX Symposium on Networked Systems Design and Implementation (NSDI)
- Gangidi, A., et al. (2024). “RDMA over Ethernet for Distributed Training at Meta Scale.” Proceedings of the ACM SIGCOMM Conference
- DeepSeek-AI. (2024). “DeepSeek-V3 Technical Report.” arXiv preprint
- Khashab, S., et al. (2025). “NSX: Large-Scale Network Simulation on an AI Server” Proceedings of the ACM Conference on AI Networking