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北京时间·🕒 发布 06:49:24时区推断·⟳ 抓取 06:49:49回填·⚡ 决策 07-18 06:50:48·101.4 天前
Rambus 宣传参加 D&R IP SoC China 并做芯粒安全与 AI 推理内存架构演讲
这是公司官网活动宣传，内容是会议参展与技术演讲主题，并未披露订单、客户、收入增量、产品获批或可交易的供需变化。
📄 原文RMBS↗ 原文
D&R IP SoC China
Join us for D&R IP SoC China! Stop by and say hi to our experts, and join us for two presentations. Title: From Monolit…
不做 Rambus（RMBS.US）
公司官方活动宣传和技术演讲预告，无订单、客户、金额或产品商业化增量，不能形成同向可执行交易。
展开详情(成交明细 / 研究档案 / 原文全文 / 决策记录链)
研究档案
🔎 新鲜度:最早出现 2026-07-17 · 扩散 low · price-in 风险 low ↗
关键理由
- 这是公司官网活动宣传，内容是会议参展与技术演讲主题，并未披露订单、客户、收入增量、产品获批或可交易的供需变化。
主要风险
- 若后续会议披露具体客户设计导入、授权合同或可量化 IP 订单，需要作为新事件重新评估。
原文全文
展开原文 · 1,801 字
Join us for D&R IP SoC China! Stop by and say hi to our experts, and join us for two presentations.
Title: From Monolithic SoCs to Chiplets: A New Hardware Security Paradigm
Speaker: Samuel Chiang, Director of Business Development, APAC at Rambus
Abstract: Chiplet‑based architectures are transforming SoC design, but they also upend long‑standing security assumptions. By disaggregating a monolithic die into multiple, often multi‑vendor chiplets, the implicit silicon trust boundary disappears, expanding the attack surface to include chiplet substitution, weak‑chiplet compromise, and exposed die‑to‑die interconnects. This presentation explores why traditional SoC security models fail in chiplet systems and introduces a system‑level security paradigm based on distributed trust with centralized authority.
Title: AI Inference Needs a Mix-and-Match Memory Strategy
Speaker: Kai Zhao, SPE Field Applications Engineering
Abstract: AI inference spans diverse workloads, from low‑latency chat to long‑context reasoning and large‑scale recommendations—making single, monolithic accelerator and memory designs increasingly inefficient. This talk explains how inference naturally splits into prefill and decode stages with fundamentally different bottlenecks: prefill is compute‑bound, while decode is dominated by memory bandwidth and latency. By matching memory technologies to each stage, using cost‑efficient GDDR or LPDDR for prefill and reserving premium HBM for decode, with pooled memory for KV offload, operators can significantly reduce cost per token without sacrificing latency. The session outlines emerging disaggregated architectures for AI inference workloads.
To learn more and register, visit the event page here: https://www.design-reuse-embedded.com/ipsocdays/2026/china/
Title: From Monolithic SoCs to Chiplets: A New Hardware Security Paradigm
Speaker: Samuel Chiang, Director of Business Development, APAC at Rambus
Abstract: Chiplet‑based architectures are transforming SoC design, but they also upend long‑standing security assumptions. By disaggregating a monolithic die into multiple, often multi‑vendor chiplets, the implicit silicon trust boundary disappears, expanding the attack surface to include chiplet substitution, weak‑chiplet compromise, and exposed die‑to‑die interconnects. This presentation explores why traditional SoC security models fail in chiplet systems and introduces a system‑level security paradigm based on distributed trust with centralized authority.
Title: AI Inference Needs a Mix-and-Match Memory Strategy
Speaker: Kai Zhao, SPE Field Applications Engineering
Abstract: AI inference spans diverse workloads, from low‑latency chat to long‑context reasoning and large‑scale recommendations—making single, monolithic accelerator and memory designs increasingly inefficient. This talk explains how inference naturally splits into prefill and decode stages with fundamentally different bottlenecks: prefill is compute‑bound, while decode is dominated by memory bandwidth and latency. By matching memory technologies to each stage, using cost‑efficient GDDR or LPDDR for prefill and reserving premium HBM for decode, with pooled memory for KV offload, operators can significantly reduce cost per token without sacrificing latency. The session outlines emerging disaggregated architectures for AI inference workloads.
To learn more and register, visit the event page here: https://www.design-reuse-embedded.com/ipsocdays/2026/china/
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