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北京时间·🕒 发布 05:27:18时区推断·⟳ 抓取 05:27:56·⚡ 决策 07-23 05:30:09 +2m13s·96.5 天前
Rambus发布韩国D&R IP SoC活动参会与演讲预告
这是一条公司官方活动宣传，内容为邀请参会和两场技术演讲摘要，没有披露订单、客户、财务指引、产品商业化进展或可量化增量。
📄 原文RMBS↗ 原文
D&R IP SoC South Korea
Join us for D&R IP SoC South Korea! Stop by and say hi to our experts, and join us for two presentations. Title: From M…
不做 Rambus（RMBS.US）
公司官方活动宣传和演讲摘要，不涉及订单、客户、收入、利润或供需约束变化，无法形成可回测交易催化。
展开详情(成交明细 / 研究档案 / 原文全文 / 决策记录链)
研究档案
🔎 新鲜度:最早出现 2026-07-22 · 扩散 low · price-in 风险 low ↗
关键理由
- 这是一条公司官方活动宣传，内容为邀请参会和两场技术演讲摘要，没有披露订单、客户、财务指引、产品商业化进展或可量化增量。
主要风险
- 无可执行同向交易信号；若后续活动披露真实客户、订单或新产品商业化信息，应按新事件重新研判。
原文全文
展开原文 · 1,805 字
Join us for D&R IP SoC South Korea! Stop by and say hi to our experts, and join us for two presentations.
Title: From Monolithic SoCs to Chiplets: A New Hardware Security Paradigm
Speaker: Jong Han Won, SPE Field Applications Engineering at Rambus
Abstract: Chiplet‑based architectures are transforming SoC design, but they also upend long‑standing security assumptions. By disaggregating a monolithic die into multiple, often multi‑vendor chiplets, the implicit silicon trust boundary disappears, expanding the attack surface to include chiplet substitution, weak‑chiplet compromise, and exposed die‑to‑die interconnects. This presentation explores why traditional SoC security models fail in chiplet systems and introduces a system‑level security paradigm based on distributed trust with centralized authority.
Title: AI Inference Needs a Mix-and-Match Memory Strategy
Speaker: Suk Keun Youn, Director, Silicon IP at Rambus
Abstract: AI inference spans diverse workloads, from low‑latency chat to long‑context reasoning and large‑scale recommendations—making single, monolithic accelerator and memory designs increasingly inefficient. This talk explains how inference naturally splits into prefill and decode stages with fundamentally different bottlenecks: prefill is compute‑bound, while decode is dominated by memory bandwidth and latency. By matching memory technologies to each stage, using cost‑efficient GDDR or LPDDR for prefill and reserving premium HBM for decode, with pooled memory for KV offload, operators can significantly reduce cost per token without sacrificing latency. The session outlines emerging disaggregated architectures for AI inference workloads.
To learn more and register, visit the event page here: https://www.design-reuse-embedded.com//ipsocdays/2026/korea/
Title: From Monolithic SoCs to Chiplets: A New Hardware Security Paradigm
Speaker: Jong Han Won, SPE Field Applications Engineering at Rambus
Abstract: Chiplet‑based architectures are transforming SoC design, but they also upend long‑standing security assumptions. By disaggregating a monolithic die into multiple, often multi‑vendor chiplets, the implicit silicon trust boundary disappears, expanding the attack surface to include chiplet substitution, weak‑chiplet compromise, and exposed die‑to‑die interconnects. This presentation explores why traditional SoC security models fail in chiplet systems and introduces a system‑level security paradigm based on distributed trust with centralized authority.
Title: AI Inference Needs a Mix-and-Match Memory Strategy
Speaker: Suk Keun Youn, Director, Silicon IP at Rambus
Abstract: AI inference spans diverse workloads, from low‑latency chat to long‑context reasoning and large‑scale recommendations—making single, monolithic accelerator and memory designs increasingly inefficient. This talk explains how inference naturally splits into prefill and decode stages with fundamentally different bottlenecks: prefill is compute‑bound, while decode is dominated by memory bandwidth and latency. By matching memory technologies to each stage, using cost‑efficient GDDR or LPDDR for prefill and reserving premium HBM for decode, with pooled memory for KV offload, operators can significantly reduce cost per token without sacrificing latency. The session outlines emerging disaggregated architectures for AI inference workloads.
To learn more and register, visit the event page here: https://www.design-reuse-embedded.com//ipsocdays/2026/korea/
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