📰 DigiTimesDigiTimesDoubao · 实盘不做把握 7/10不做原因:标的无直接敞口
北京时间·🕒 发布 09-11 06:03:19·⟳ 抓取 09-11 06:14:40 +11m21s·⚡ 决策 09-15 13:04:07 +4d06h·42.4 天前
d-Matrix 宣布采用英伟达 NVLink Fusion 将下一代 Raptor 推理 XPU 接入 MGX 机架，2027Q4 才上市，直接主体未上市、合作方无实质订单
事件直接受益主体 d-Matrix 未上市；唯一被点名的上市公司 Astera Labs 仅有不具金额的早期合作表述、且本就是该生态既有伙伴，对其无 material 增量；NVIDIA 作为平台方市值巨大、事件无量级；Raptor 2027Q4 才供货，距今 1 年以上无订单无收入。消息距今 103 小时，已被 NVIDIA 官方博客、DigiTimes、Unite.AI、CoinDesk 等多源扩散，且 ALAB 9/14 大跌 11.74% 表明市场未将其解读为利好。
📄 原文DigiTimes↗ 原文
GPU economics face pressure as token prices fall, d-Matrix says
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不做 Astera Labs（ALAB.US）
无金额、无收入口径的早期生态合作提及，公司本就是 NVLink Fusion 既有伙伴；事件已扩散 103 小时且官方博客后股价无正向反应、9/14 反跌 11.74%，无因果收入敞口与剩余 edge。
不做 NVIDIA（NVDA.US）
第三方初创接入其开放互连生态对万亿市值主体无订单/指引增量，属无 materiality 的软催化。
不做 d-Matrix（未上市）及未点名 3D DRAM 供应商（N/A）
d-Matrix 为微软支持的私营公司、无任何可交易证券；Raptor 所用 3D DRAM 供应商未点名，无法坐实二阶 A 股/海外映射标的，不凭记忆硬接。
展开详情(成交明细 / 研究档案 / 原文全文 / 决策记录链)
研究档案
结论摘要
这是一条私营初创的生态集成技术新闻：产品 2027Q4 才上市、无订单金额，被点名的上市公司 Astera Labs 仅获一句合作表述且近期反随大盘下跌，没有任何可交易主体具备可量化的因果收入敞口，故不做。
消息传播链
- NVIDIA 官方 2026-09-10 即发布博客确认 d-Matrix 采用 NVLink Fusion 接入 MGX，属公司一手披露，与 DigiTimes 同日；说明并非媒体独家爆料，传播起点即官方公开信息。
- DigiTimes 9/11 06:03 刊发并于 13:50 更新，补充 d-Matrix 成本模型、3D DRAM 规格与 Astera 合作细节；时点晚于 NVIDIA 官方博客。
- 9/11–9/13 多家英文科技媒体跟进，扩散度高；至研判时已 103 小时，无任何后续订单/金额升级。市场反应:ALAB 9/11 +2.35%（弱反应），9/14 -11.74%（随其他因素下跌），无正向事件定价痕迹。
关键理由
- 直接主体 d-Matrix 未上市，生态方 NVIDIA 无量级，合作方 Astera Labs 无合同金额，整条链路不存在 material 的可交易受益标的
主要风险
- 若后续 d-Matrix 公布上市计划或向 Astera 下达有金额量产合同，结论需重估；9/14 ALAB -11.74% 的具体催化（疑似财报）未在本轮核实，不应反向解读为本事件利空
反向证据
- 做多前查反向 · 来源 web · 日期 2026-09-14 · 影响 weakens
ALAB 9/14 单日 -11.74%、20 日累计 -20.08%，处于下行通道；官方博客后 9/11 仅 +2.35%，市场未将 d-Matrix 合作定价为利好，做多逻辑被价格行为否证
检索:ALAB 行情与 2026-09-14 大跌原因/近期利空 - 做多前查反向 · 来源 web · 日期 2026-09-11 · 影响 invalidates
所有报道仅表述『working with on custom solutions』，无 design win 金额、无 backlog、无量产承诺，且供货在 2027Q4，无法建立近期收入敞口
检索:d-Matrix Astera Labs contract revenue design win amount 原文 ↗
先例如何影响了这次决策
对本次决策的影响:支持 AVOID：不据此开多 Astera Labs 或任何二阶映射标的
方向:无可直接对齐的可交易受益主体，事件对上市公司的量级接近于零，先例统计不会改变 NO_CAUSAL_EXPOSURE 结论，故不构造面板
涨幅量级:不适用：无 ENTER 候选，无需校准 tp/sl
形态:观察性证据：被点名的 Astera Labs 在官方博客后首个交易日仅 +2.35%、次交易日 -11.74%，与『生态合作软催化见光死/无定价』方向一致
工具执行结果 · 成功 3 · 降级 0 · 失败 0 · 取消 0
- search_processed_events 成功 stock_tools HTTP · 17 ms
{"result": "search_processed_events:agent query=`d-matrix astera labs raptor 3d dram partnership | d-matrix nvidia nvlink fusion 推理芯片 机架 | d-matrix raptor nvlink fusion nvidia mgx rack inference`；结构化索引覆盖完整 72 小时；旧记录兼容扫描近 0.0/72 小时、0 条本臂决策(完整)，返回 0 条候选。未命中只表示这些 agent query 表达式没有召回候选，不能据此证明消息首发或不是重复；按 - web_search 成功 doubao_search · 1,619 ms
豆包搜索结果（原始查询:d-Matrix Raptor Astera Labs NVLink Fusion MGX announcement；API SearchType:web） - stock_quote 成功 stock_tools HTTP · 86 ms
{
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d-Matrix brings Raptor chips to Nvidia racks as falling token prices pressure GPU economics
Sherri Wang
, DIGITIMES, Taipei
Sep 11, 2026, 06:03 , Updated: Sep 11, 2026, 13:50
0
d-Matrix plans to integrate its Raptor inference processors into Nvidia MGX racks using NVLink Fusion. Credit: Nvidia
AI chip startup d-Matrix is adopting Nvidia's NVLink Fusion technology to bring its next-generation Raptor inference processors into Nvidia MGX racks, giving the company a path into an established data center ecosystem as it targets low-latency AI inference.
Raptor is expected to tape out before the end of 2026, with initial availability in Nvidia MGX racks targeted for the fourth quarter of 2027. d-Matrix said the integration will allow customers to deploy Raptor within Nvidia's broadly deployed liquid-cooled infrastructure rather than build a separate rack-scale infrastructure stack around the accelerator.
The Microsoft-backed startup is also working with connectivity specialist Astera Labs on custom solutions designed to maintain high-speed data movement across the system.
The collaboration comes as AI workloads increasingly shift from model training toward inference, where prefill, decode and other stages can place very different demands on compute, memory and networking resources.
At the SEMICON Taiwan 2026 Memory Executive Summit, d-Matrix Vice President Chris Nicol argued that those differences are becoming increasingly important as falling token prices put pressure on the economics of GPU-based inference.
Nicol presented a cost model showing that market pricing for output tokens from a Llama 70B model could fall below d-Matrix's estimated H200 decode cost floor around 2027. He argued that the challenge is not whether installed GPUs can run the workloads, but whether they can remain economically competitive as newer accelerators push token costs lower.
He pointed to Nvidia's B300 as an example of a newer generation that could increase pressure on operators to refresh older GPU fleets.
The figures represent d-Matrix's own workload model rather than an independent industry benchmark.
d-Matrix Vice President Chris Nicol presents an inference cost model at the SEMICON Taiwan 2026 Memory Executive Summit. Credit: Sherri Wang
Decode widens GPU utilization gap
d-Matrix argues that the pressure reflects a broader mismatch between general-purpose GPU architectures and the increasingly diverse requirements of AI inference.
Prefill, decode, attention and mixture-of-experts (MoE) workloads can have sharply different compute and memory characteristics, making it difficult for a single type of processor to operate efficiently across every phase.
Most modern GPUs have an arithmetic-intensity "ridge point" above 1,000 floating-point operations per byte, according to Nicol. Prefill can approach that level because prompts are processed in parallel and the workload is relatively compute-intensive.
Decode is much more memory-bound. Generating each token requires repeatedly accessing model weights and the key-value cache while performing comparatively little computation, putting its arithmetic intensity at roughly 2 to 100 FLOPs per byte.
Nicol showed the ridge point moving higher from Nvidia's H200 through the B200 and GB300 as compute performance increases faster than memory bandwidth.
Increasing batch sizes can improve GPU utilization, but the approach eventually runs into another constraint. Larger batches expand the KV cache for each user, increasing memory traffic until further batching no longer raises arithmetic intensity enough to fully utilize the GPU.
The result, according to d-Matrix, is a persistent utilization gap for decode workloads even as peak GPU computing power continues to rise.
Raptor targets heterogeneous inference
Rather than replacing GPUs outright, d-Matrix sees an opportunity to move memory-bound portions of inference onto processors optimized for lower arithmetic intensity.
The Nvidia collaboration provides a more concrete path for that strategy by allowing Raptor processors to operate within Nvidia-based data center systems using NVLink Fusion.
Nvidia introduced NVLink Fusion to allow custom CPUs and accelerators to connect to its rack-scale infrastructure, opening its high-speed interconnect ecosystem beyond systems built exclusively around Nvidia processors.
For d-Matrix, that means its inference-focused accelerators can potentially operate alongside GPUs rather than requiring data center operators to build a completely separate infrastructure stack.
One example presented by Nicol is speculative decoding, where a smaller draft model generates candidate tokens that are subsequently verified by a larger target model. Running the draft stage on high-end GPUs can be inefficient because the workload does not fully use their computing resources, he said.
For a 70-billion-parameter model, d-Matrix presented a configuration in which adding SRAM-based accelerators to a GPU fleet increased operating costs by about 20% while delivering roughly four times the throughput and lowering modeled cost by about 70%.
Nicol said the approach could increase the productivity of installed GPU infrastructure and reduce pressure to replace entire fleets each time a newer accelerator generation arrives.
d-Matrix's current Corsair inference accelerator entered full production earlier this year, with volume shipments targeting hyperscalers, neoclouds and frontier AI labs. Raptor represents the company's next generation and extends its memory-centric approach with vertically stacked 3D DRAM.
At Hot Chips 2026, d-Matrix presented a rack-scale Raptor configuration providing 2.3TB of vertically mounted DRAM and 7.2PB/s of aggregate bandwidth. Individual cards were described as providing 32GB of memory and 100TB/s of bandwidth.
d-Matrix's Raptor scales 3D DRAM to 2.3TB and 7.2PB/s. Credit: Sherri Wang
Networking becomes part of memory architecture
Disaggregating inference creates another challenge: networking increasingly becomes part of the memory architecture itself.
Nicol said transfers between specialized processors ultimately need to terminate as close as possible to the target processor's on-chip memory. Moving data through multiple layers of DRAM and host memory adds latency that can undermine the efficiency gained by splitting workloads across specialized hardware.
The longer-term target, he said, is a direct SRAM-to-network-to-SRAM architecture.
d-Matrix argues that disaggregated inference will require low-latency transfers directly between on-chip SRAM across the network. Credit: Sherri Wang
d-Matrix argues that disaggregated inference will require low-latency transfers directly between on-chip SRAM across the network. Credit: Sherri Wang
Such systems would require predictable latency, explicit addressability and standardized memory mapping across the fabric. Nicol said the industry does not yet have a standardized fabric capable of providing the direct SRAM-to-SRAM transfer model envisioned by d-Matrix.
NVLink Fusion nevertheless gives the company an existing high-speed interconnect ecosystem through which Raptor can be integrated with Nvidia-based infrastructure.
MoE architectures further increase the importance of the network. Separating attention processing from expert computation can improve utilization across different hardware pools, but also turns part of the memory bottleneck into a routing problem as data moves between workers at every model layer.
The shift could also change the role of memory suppliers.
Memory increasingly intersects with processor design, packaging, interconnect, runtime software and model architecture, Nicol said, creating an opportunity for suppliers to participate earlier in system design rather than simply providing capacity and bandwidth.
For d-Matrix, the Nvidia collaboration suggests heterogeneous inference may develop not by displacing GPU infrastructure, but by inserting specialized accelerators into the rack-scale ecosystems surrounding it.
As inference workloads diversify and token prices fall, Nicol argues that peak FLOPs alone will become a less useful measure of efficiency. Sustained token generation will increasingly depend on co-designing compute, memory, networking and software around the requirements of individual stages of the inference pipeline.
Article
edited by Jerry Chen
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Tomorrow's Headlines
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Home
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d-Matrix brings Raptor chips to Nvidia racks as falling token prices pressure GPU economics
Sherri Wang
, DIGITIMES, Taipei
Sep 11, 2026, 06:03 , Updated: Sep 11, 2026, 13:50
0
d-Matrix plans to integrate its Raptor inference processors into Nvidia MGX racks using NVLink Fusion. Credit: Nvidia
AI chip startup d-Matrix is adopting Nvidia's NVLink Fusion technology to bring its next-generation Raptor inference processors into Nvidia MGX racks, giving the company a path into an established data center ecosystem as it targets low-latency AI inference.
Raptor is expected to tape out before the end of 2026, with initial availability in Nvidia MGX racks targeted for the fourth quarter of 2027. d-Matrix said the integration will allow customers to deploy Raptor within Nvidia's broadly deployed liquid-cooled infrastructure rather than build a separate rack-scale infrastructure stack around the accelerator.
The Microsoft-backed startup is also working with connectivity specialist Astera Labs on custom solutions designed to maintain high-speed data movement across the system.
The collaboration comes as AI workloads increasingly shift from model training toward inference, where prefill, decode and other stages can place very different demands on compute, memory and networking resources.
At the SEMICON Taiwan 2026 Memory Executive Summit, d-Matrix Vice President Chris Nicol argued that those differences are becoming increasingly important as falling token prices put pressure on the economics of GPU-based inference.
Nicol presented a cost model showing that market pricing for output tokens from a Llama 70B model could fall below d-Matrix's estimated H200 decode cost floor around 2027. He argued that the challenge is not whether installed GPUs can run the workloads, but whether they can remain economically competitive as newer accelerators push token costs lower.
He pointed to Nvidia's B300 as an example of a newer generation that could increase pressure on operators to refresh older GPU fleets.
The figures represent d-Matrix's own workload model rather than an independent industry benchmark.
d-Matrix Vice President Chris Nicol presents an inference cost model at the SEMICON Taiwan 2026 Memory Executive Summit. Credit: Sherri Wang
Decode widens GPU utilization gap
d-Matrix argues that the pressure reflects a broader mismatch between general-purpose GPU architectures and the increasingly diverse requirements of AI inference.
Prefill, decode, attention and mixture-of-experts (MoE) workloads can have sharply different compute and memory characteristics, making it difficult for a single type of processor to operate efficiently across every phase.
Most modern GPUs have an arithmetic-intensity "ridge point" above 1,000 floating-point operations per byte, according to Nicol. Prefill can approach that level because prompts are processed in parallel and the workload is relatively compute-intensive.
Decode is much more memory-bound. Generating each token requires repeatedly accessing model weights and the key-value cache while performing comparatively little computation, putting its arithmetic intensity at roughly 2 to 100 FLOPs per byte.
Nicol showed the ridge point moving higher from Nvidia's H200 through the B200 and GB300 as compute performance increases faster than memory bandwidth.
Increasing batch sizes can improve GPU utilization, but the approach eventually runs into another constraint. Larger batches expand the KV cache for each user, increasing memory traffic until further batching no longer raises arithmetic intensity enough to fully utilize the GPU.
The result, according to d-Matrix, is a persistent utilization gap for decode workloads even as peak GPU computing power continues to rise.
Raptor targets heterogeneous inference
Rather than replacing GPUs outright, d-Matrix sees an opportunity to move memory-bound portions of inference onto processors optimized for lower arithmetic intensity.
The Nvidia collaboration provides a more concrete path for that strategy by allowing Raptor processors to operate within Nvidia-based data center systems using NVLink Fusion.
Nvidia introduced NVLink Fusion to allow custom CPUs and accelerators to connect to its rack-scale infrastructure, opening its high-speed interconnect ecosystem beyond systems built exclusively around Nvidia processors.
For d-Matrix, that means its inference-focused accelerators can potentially operate alongside GPUs rather than requiring data center operators to build a completely separate infrastructure stack.
One example presented by Nicol is speculative decoding, where a smaller draft model generates candidate tokens that are subsequently verified by a larger target model. Running the draft stage on high-end GPUs can be inefficient because the workload does not fully use their computing resources, he said.
For a 70-billion-parameter model, d-Matrix presented a configuration in which adding SRAM-based accelerators to a GPU fleet increased operating costs by about 20% while delivering roughly four times the throughput and lowering modeled cost by about 70%.
Nicol said the approach could increase the productivity of installed GPU infrastructure and reduce pressure to replace entire fleets each time a newer accelerator generation arrives.
d-Matrix's current Corsair inference accelerator entered full production earlier this year, with volume shipments targeting hyperscalers, neoclouds and frontier AI labs. Raptor represents the company's next generation and extends its memory-centric approach with vertically stacked 3D DRAM.
At Hot Chips 2026, d-Matrix presented a rack-scale Raptor configuration providing 2.3TB of vertically mounted DRAM and 7.2PB/s of aggregate bandwidth. Individual cards were described as providing 32GB of memory and 100TB/s of bandwidth.
d-Matrix's Raptor scales 3D DRAM to 2.3TB and 7.2PB/s. Credit: Sherri Wang
Networking becomes part of memory architecture
Disaggregating inference creates another challenge: networking increasingly becomes part of the memory architecture itself.
Nicol said transfers between specialized processors ultimately need to terminate as close as possible to the target processor's on-chip memory. Moving data through multiple layers of DRAM and host memory adds latency that can undermine the efficiency gained by splitting workloads across specialized hardware.
The longer-term target, he said, is a direct SRAM-to-network-to-SRAM architecture.
d-Matrix argues that disaggregated inference will require low-latency transfers directly between on-chip SRAM across the network. Credit: Sherri Wang
d-Matrix argues that disaggregated inference will require low-latency transfers directly between on-chip SRAM across the network. Credit: Sherri Wang
Such systems would require predictable latency, explicit addressability and standardized memory mapping across the fabric. Nicol said the industry does not yet have a standardized fabric capable of providing the direct SRAM-to-SRAM transfer model envisioned by d-Matrix.
NVLink Fusion nevertheless gives the company an existing high-speed interconnect ecosystem through which Raptor can be integrated with Nvidia-based infrastructure.
MoE architectures further increase the importance of the network. Separating attention processing from expert computation can improve utilization across different hardware pools, but also turns part of the memory bottleneck into a routing problem as data moves between workers at every model layer.
The shift could also change the role of memory suppliers.
Memory increasingly intersects with processor design, packaging, interconnect, runtime software and model architecture, Nicol said, creating an opportunity for suppliers to participate earlier in system design rather than simply providing capacity and bandwidth.
For d-Matrix, the Nvidia collaboration suggests heterogeneous inference may develop not by displacing GPU infrastructure, but by inserting specialized accelerators into the rack-scale ecosystems surrounding it.
As inference workloads diversify and token prices fall, Nicol argues that peak FLOPs alone will become a less useful measure of efficiency. Sustained token generation will increasingly depend on co-designing compute, memory, networking and software around the requirements of individual stages of the inference pipeline.
Article
edited by Jerry Chen
AI Search
Related stories
Sambanova challenges GPU dominance in AI inference at Computex
Memory bottlenecks threaten data-center GPU efficiency as AI inference scales, says Micron SVP
AI Expo 2026: Surging costs, memory crunch drive shift toward inference, researcher says
SambaNova targets Nvidia’s B200 with 5x faster AI inference chip, secures US$350M
Nvidia's Rubin CPX GPU revolutionizes AI inference while reshaping memory supply chains
Show more
Categories
Chips + components IC design, distribution Server, IPC, cloud computing, IoT
Tags
AI inference cost data center DRAM GPU hardware Nvidia
Share this article
Other links
Related topics
Global supply chain: Key components
Global supply chain: Mobile, telecom, computing
Semicon Taiwan 2026
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Sep 14, 08:00
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Monday 14 September 2026
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