格芯德累斯顿SPRINT封顶并发布FDX Fusion：无EUV的7nm级FD-SOI路线，但量产在2028且以政府审批为前提

GlobalFoundries' plan to build a 7nm-class chip process in Dresden without extreme ultraviolet (EUV) lithography tests how a second-tier foundry can stay relevant while TSMC holds most of the AI data center market. Instead of competing on transistor size, GF is competing on integration, power efficiency, and location, and it is making European supply security part of its pitch.

On October 9, 2026, the US-based contract chipmaker held a topping-out ceremony for its EUR1.1 billion (US$1.23 billion) SPRINT expansion in Dresden and unveiled FDX Fusion, the next generation of its fully depleted silicon-on-insulator (FD-SOI) technology. GF said the expansion will lift the site's annual capacity from up to 950,000 12-inch wafers, depending on product mix, to more than one million by the end of 2028, making Dresden Europe's largest foundry site. The company plans to start FDX Fusion manufacturing there in 2028.
Sidestepping the leading-edge race
TSMC captured nearly 70% of global foundry revenue in 2025, while GlobalFoundries, UMC, and SMIC together held about 13.5%. GF canceled its own 7nm FinFET program in 2018 and repositioned itself as a specialty foundry. The outlet reported that GF's 2025 revenue rose 1% to US$6.79 billion.
Manfred Horstmann, general manager and senior vice president at GF, described the new platform as a deliberate detour. "The data center AI train has left the station," he told EE Times . "But for physical AI, the world is still open."
Physical AI covers robots, vehicles, drones, and industrial machines that must sense and act in real time. Horstmann said such systems need "sensors, actuators, communications, low power, and cost efficiency," not only compute. GF said the first generation of FDX Fusion will deliver 7nm-class digital performance and more than twice the density of its first-generation FDX technology. The same process will also offer RF performance of up to 0.5 THz ft/fmax, analog and mixed-signal functions, and embedded non-volatile memory.
A cheaper route to 7nm-class performance
Cost is central to the pitch. "For 7nm-class performance, we don't need EUV," Horstmann said. EE Times reported that GF expects the initial process to need about 50 masks, compared with the 70 to 80 masks Horstmann cited for advanced 2nm and 3nm FinFET processes. Instead of EUV, GF will rely on ArF immersion lithography and high-precision masks from Dresden-based mask maker AMTC.
Horstmann said GF expects to invest roughly US$1 billion in FDX Fusion development over the coming years, including about US$250 million for the initial toolset. GF is targeting demonstrator silicon for early 2027 and an initial process design kit (PDK) for mid-2027.
GF is also trying to sell more than wafers. It offers MIPS and ARC processor IP and RISC-V design capabilities alongside its processes. Tom's Hardware said no other trailing-edge foundry currently offers this combination, and that it could especially help smaller fabless developers that lack their own processor IP.
Courting ESMC's backers
GF's customer list points to the competitor it has in mind. The announcement carried supportive statements from BMW, Bosch, Infineon, NXP, Siemens, and Tesla. However, Tom's Hardware noted that only Infineon specifically confirmed collaboration on future 7nm-class technologies for radar and wireless communication products.
Bosch, Infineon, and NXP are also TSMC's partners in the European Semiconductor Manufacturing Company (ESMC), a joint venture building its own fab in Dresden. German tech outlet heise said GF's naming of those three companies was "hardly a coincidence." ESMC held its topping-out ceremony on September 14 and expects to install its first process equipment in the second half of 2027.
Horstmann called ESMC a competitor. He also said it strengthens the Dresden ecosystem by adding scale to the region and making it more attractive to suppliers.
Sovereignty as a selling point
GF's Dresden strategy is closely tied to European industrial policy. The EU, the German federal government, and the Free State of Saxony support the SPRINT expansion under the European Chips Act. GF said the expansion will let it offer "Europe-only processes and data flows" for customers with stringent security requirements, including critical infrastructure and aerospace customers.
Tom's Hardware said FDX Fusion could give European semiconductor developers access to a more advanced locally manufactured process "without dependence on leading-edge foundries in Asia or the US." The outlet described GF as becoming a US and European specialty foundry. Geography is also shaping its mature-node peers: UMC is developing a 12nm FinFET node with Intel for 2027 production in Arizona, and SMIC is expanding mature-node capacity in China under tightening export controls.
Horstmann presented the platform as a European opportunity as much as a corporate one. "This is a big opportunity for Europe to define a new market," he said, "and to be first."
Conditions and a mixed record
The plan comes with conditions. GF said FDX Fusion development will only actually start once the German federal government approves GF Dresden's project start under the Important Project of Common European Interest on Advanced Semiconductor Technologies (IPCEI AST), a European funding framework.
GF also has a mixed record on FD-SOI scaling. It announced 12FDX in 2016 and expected the first customer tape-outs in 2019, but the node was never adopted for commercial products. The outlet noted that GF's announcement did not disclose transistor dimensions or pitch figures. However, Horstmann separately told EE Times he expects logic density of roughly 14 million to 18 million gates per square millimeter. Tom's Hardware also said commercial success will depend on a competitive design ecosystem, with this "arguably being the hardest part," given the lack of comments from leading electronic design automation (EDA) and IP developers.