DigiTimes援引SemiAnalysis专利分析称ASML或在研发D2W混合键合机，潜在挑战Besi，但无官方产品、商业化遥远

As it becomes harder and costlier to shrink transistors, advanced packaging has become the place chip equipment makers look to for their next leg of growth, and ASML appears to be preparing its second move into it. Patent filings analyzed by research firm SemiAnalysis suggest the Dutch lithography leader is building a die-to-wafer (D2W) hybrid bonder, a tool that would pit it against Besi, the current leader, and a growing group of front-end rivals chasing the same market.

Hybrid bonding stacks chips by joining their copper pads directly, rather than through solder bumps, allowing far denser connections between dies. Wafer-to-wafer bonding is already in volume production for image sensors and 3D NAND. By contrast, die-to-wafer bonding, which places individual dies onto a wafer, runs in volume only in advanced logic, according to SemiAnalysis.
A bonder that runs on a track
ASML has not announced a bonding product. The Elec reported in March 2026 that ASML began architectural design of a hybrid bonding system with longtime suppliers Prodrive Technologies and VDL ETG, though ASML said it had not officially started any hybrid bonding business. SemiAnalysis counted 27 bonding patent families filed by ASML between December 2022 and November 2024, most of them for D2W bonding.
The anchor filing, WO2025201788A1, describes a machine unlike today's bonders. Instead of a bond head picking each die off a diced wafer, every die rides on its own holder around a track, stopping at inspection, cleaning, plasma activation, and alignment stations before a chuck lifts the bottom wafer up to meet it. SemiAnalysis said the layout lets capacity grow by adding stations rather than whole tools, but that ASML still has to solve feed-forward metrology, die-to-wafer contact, and cleanliness across the whole loop.
Why packaging, and why now
"Moore's Law is slowing," Chris Scanlan, senior VP of technology at Besi, told EE Times in November 2025, adding that once a chip is split into smaller dies, "you need an interconnect technology with very high density, very low loss, and very tight pitch." Reuters described advanced packaging in March 2026 as "currently a key bottleneck for the industry."
ASML has been edging toward that bottleneck. It shipped its first packaging product, the TWINSCAN XT:260 i-line scanner, in the third quarter of 2025. According to All About Industries , ASML CTO Marco Pieters told Reuters in an interview that ASML was researching how far it could participate in this part of the business, with packaging and bonding playing a special role.
A growing field of rivals
ASML would not be the only front-end toolmaker reaching into bonding. Applied Materials co-developed the Kinex integrated D2W system with Besi and bought a 9% stake in the Dutch company in April 2025, becoming its largest shareholder. Reuters reported in March 2026, citing people familiar with the matter, that Lam Research had discussed a potential acquisition with Besi and that Applied was also a potential suitor. Besi declined to comment on "market rumors" and said it remained committed to its strategy as an independent company. In South Korea, Hanwha Semitech's second-generation SHB2 Nano bonder was manufactured in the Netherlands by Prodrive, the same supplier said to be working with ASML, The Elec reported.
Besi is the most exposed. SemiAnalysis called it the only supplier with D2W tools in volume production, with most of its hybrid bonding business in logic and concentrated at TSMC and Intel, and expects advanced logic to adopt an ASML tool first. The firm also believes HBM will not adopt D2W hybrid bonding before 2029, if at all**. Reuters ** noted that Besi shares fell sharply in February on reports that memory makers might delay hybrid bonding in favor of thermal compression bonding. Besi is raising the bar: Scanlan said its next-generation bonder, due in 2026, aims for "50nm accuracy or better," compared with today's 100nm alignment requirement.
What it means for TSMC
TSMC is the customer most likely to feel the change first. Its SoIC 3D stacking platform bonds at a pitch of about 6 microns today and targets 4.5 microns around 2029. The foundry calls overlay "always the biggest challenge" for SoIC, according to SemiAnalysis, which argues that tighter placement is where ASML's lithography alignment experience would count most.
The stakes rise with capacity. TrendForce, citing supply chain sources, reported that TSMC plans SoIC capacity of about 10,000 to 15,000 wafers per month by 2026, with institutional investors estimating capital spending of about US$6.8-7.0 billion per 10,000 wafers, significantly higher per unit than CoWoS. The report said Besi, Applied Materials, and Tokyo Electron would benefit first, and that Taiwanese companies may find openings in wet processing and equipment.
An ASML bonder could also be sold alongside its scanners. A July 2024 ASML filing describes the bonder handing each die's position map to the scanner, which then checks only a few marks before exposure, rather than aligning every die on a bonded wafer. ASML, TSMC, Intel Foundry, and Samsung announced in September an initiative to move High NA EUV to 12-inch photomasks, and SemiAnalysis said it "won't be surprised to see a similar move in the back-end process."