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📰 DigiTimesDigiTimesDoubao · 实盘不做把握 7/10不做原因:风险收益比不佳
北京时间·🕒 发布 07:22:10·⟳ 抓取 07:32:09 +9m59s·⚡ 决策 10-20 07:34:08 +1m59s·7.4 天前

SK海力士在OCP峰会展示MARS内存池化架构与HBF新内存层,HBF硬件要到2028年才送样

这是一场OCP会议上的架构演示与早期规范发布:性能数字来自demo/合作测试,软件栈仍处产学研共建,HBF规范仅v0.7、硬件2028年前后才送样,没有客户定点、订单、backlog或指引上调等需求验证。直接主体SK海力士是超大市值公司,纯技术愿景对其短期收入/市值无可交易增量;CXL/内存接口映射标的也未获点名或订单,方向虽偏正面但无近期正期望。

📄 原文DigiTimes↗ 原文
SK Hynix moves AI data centers from processor-centric to memory-centric design
SK Hynix has presented the Memory-Centric AI Rack System (MARS) at the Open Compute Project (OCP) Global Summit. The ar…
不做 SK Hynix(000660.KS)
OCP会议技术演示+早期规范(v0.7),HBF硬件2028年才送样,无客户定点/订单/收入增量;对超大市值主体为软催化,无短期可交易edge,不做多也不具备做空理由
不做 SanDisk(SND.US)
仅共同发布HBF规范,无采购金额或收入承诺,纯生态层面合作,量级不可估
不做 Astera Labs(ALAB.US)
CXL互连主题外推,事件未点名、无设计定点或订单,需求未验证
展开详情(成交明细 / 研究档案 / 原文全文 / 决策记录链)

研究档案

结论摘要

SK海力士MARS+HBF是面向2027-2028的早期内存架构发布,只有演示性能与规范进展、无商用采用或订单,对超大市值主体及二阶CXL供应链都不构成可交易的短期催化,故回避。

🔎 新鲜度:最早出现 2026-10-19 · 扩散 low · price-in 风险 low ↗

关键理由

  • MARS用CXL在机架级池化DRAM、HBF填补HBM与SSD之间的内存层级,方向上强化SK海力士在AI内存架构的长期卡位
  • 但发布内容止于demo性能数据、研究合作与v0.7规范,硬件送样在2028年,缺少客户采用/订单/收入这一需求验证环节

主要风险

  • 若随后出现具体超大规模云厂商或OEM的MARS/HBF商用部署、设计定点或采购公告,本‘无需求验证’判断需重估
  • CXL内存池化若被竞争对手(三星、美光)更快商用,SK海力士的先发演示未必转化为份额

反向证据

  • 做多前查反向 · 来源 web · 日期 2026-10-19 · 影响 invalidates
    正文及事件信息中无客户采用、设计定点、订单或指引上调;这是做多逻辑最关键的缺失项,需求侧未经验证
    检索:SK Hynix MARS HBF customer design win order commercial deployment 2026 原文 ↗

先例如何影响了这次决策

方向:无可用于校准的对齐先例;且本事件为无收入、2028年才送样的早期技术演示,不进入ENTER,无需用先例校准涨幅

涨幅量级:不足,亦无必要——决策在materiality/需求验证层面即被否决

形态:半导体新架构/规范发布在缺少客户定点时通常不构成超大市值公司的短期驱动,但本轮未为此调用先例面板

工具执行结果 · 成功 1 · 降级 0 · 失败 0 · 取消 0
  1. search_processed_events 成功 stock_tools HTTP · 11 ms
    {"result": "search_processed_events:agent query=`sk hynix hbf high bandwidth flash ocp specification v0.7 sandisk | sk hynix mars memory-centric ai rack ocp cxl | sk海力士 mars cxl 内存池 hbf`;结构化索引覆盖完整 72 小时;旧记录兼容扫描近 0.0/72 小时、0 条本臂决策(完整),返回 0 条候选。未命中只表示这些 agent query 表达式没有召回候选,不能据此证明消息首发或不是重复;按当前事件继续正常研

原文全文

展开原文 · 4,302 字
SK Hynix has presented the Memory-Centric AI Rack System (MARS) at the Open Compute Project (OCP) Global Summit. The architecture separates memory from individual servers and pools it at the rack level over Compute Express Link (CXL) fabrics. The company says this addresses the capacity and cost limits that are constraining the growth of large AI models.

Hoshik Kim, Senior Vice President and Fellow of Memory Systems Research at SK Hynix America, gave the presentation. He argued that today's processor-centric designs, where memory is fixed to each CPU or GPU, can't keep pace with large language models (LLMs) and multi-turn agentic AI workloads.
"Unlocking the next level of AI performance requires fundamental changes in computer architecture... We need to rethink how data is stored, accessed, processed, and shared," Kim said.

Credit: DIGITIMES
SK hynix described several bottlenecks in current infrastructure. Adding High Bandwidth Memory (HBM) to GPUs is limited by physical space and cost, and buying extra GPUs just for memory capacity is not economical. Memory on busy nodes often runs out while memory on nearby nodes in the same cluster sits unused.
Adding memory usually means buying whole new servers, which pushes operators to over-provision costly GPU clusters. Moving data such as key-value (KV) caches between nodes over Remote Direct Memory Access (RDMA) networks also adds repeated data copying and unpredictable tail latency.
MARS turns DRAM into a shared, rack-scale pool. Capacity can be allocated, scaled, and reclaimed separately from CPU and GPU compute. CXL interconnects link compute servers and memory trays inside the rack, giving direct memory access without network overhead at the application level.
Multiple GPUs and NPUs can read one shared pool holding LLMs and context KV caches. In pipelined workloads, one accelerator can write its output to shared memory, and the next can read it directly, with no explicit transfer across an RDMA network.
SK Hynix shared performance data from three deployment scenarios. In multi-turn agentic AI workloads, offloading growing KV caches to the shared MARS pool improved time-to-first-token (TTFT) by 3.5 to 5.2 times compared with re-computation. The company said the setup virtually eliminated tail latency spikes caused by network congestion.
In a second test with AI technology partner Pickles, SK Hynix ran a full voice agent pipeline covering speech-to-text, LLM reasoning and text-to-speech. Intermediate outputs were streamed through shared CXL memory instead of over RDMA. Time-to-first-audio fell from 0.67 seconds to 0.46 seconds, 1.46 times faster. End-to-end latency fell from 8.08 seconds to 5.73 seconds, 1.41 times faster.
The third scenario was trillion-scale graph neural network (GNN) training, which usually means splitting large graphs across server nodes and waiting on frequent RDMA synchronization. Putting graph structure and feature gathering in a unified MARS pool sped up graph sampling 17.57 times compared with RDMA-based setups because the pool gives direct access at constant latency.

Credit: DIGITIMES
SK Hynix said it is co-developing a 16-tool software stack for MARS with partners from industry, government and academia. Partners include Los Alamos National Laboratory, Pacific Northwest National Laboratory, Stanford, UT Austin, the University of Illinois, Virginia Tech, UC San Diego, Carnegie Mellon, Georgia Tech and UC Berkeley/Merced. The tools cover memory allocators, inter-node locking, KV cache tiering, in-memory stores, and Graph RAG engines.
SK Hynix closed the session with High Bandwidth Flash (HBF), a memory tier that sits between HBM and enterprise SSDs.
HBF stacks 16 NAND dies with logic dies on a silicon interposer. It delivers about half the bandwidth of HBM with 10 to 14 times the capacity, and SK Hynix says it is 3.7 times more energy efficient per bit than traditional enterprise storage tiers. In demonstrations with Llama 3 70B and DeepSeek R1 671B, HBF handled context windows of up to 19 million tokens per user, according to the company.
SK Hynix said it has released the public OCP HBF Specification v0.7 with SanDisk and industry consortia. It plans to finalize Specification 1.0 next year and expects HBF Cube hardware sampling to begin around 2028.

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