event-trade登录编辑
📰 DigiTimesDigiTimesDoubao · 实盘不做把握 7/10不做原因:消息已过时
北京时间·🕒 发布 11:57:28·⟳ 抓取 12:02:15 +4m47s·⚡ 决策 10-20 12:18:10 +15m55s·7.5 天前

DigiTimes 综述:华大九天参股推动思尔芯(S2C)与亚科鸿禹(HyperSilicon)合并,补强硬件仿真验证EDA

DigiTimes文章是对10月13日董事会决议、10月14日华大九天正式公告、10月19日中文财经媒体已广泛报道事件的英文综述,无新增事实(NO_INCREMENTAL_FACT叠加STALE);直接上市主体华大九天仅为参股布局,1.5亿元现金对其约500亿市值不具materiality,且标的亚科鸿禹仍大额亏损、商业化不确定;公告窗口前后股价已有10月9日+7.96%、10月12日+6.12%两轮明显抢跑,price-in风险高,无正期望。

📄 原文DigiTimes↗ 原文
China's S2C–HyperSilicon merger targets hardware emulation gap in domestic EDA with Empyrean backing
China's electronic design automation (EDA) industry is consolidating, with Shanghai-based S2C and Wuxi-based HyperSilic…
不做 华大九天(301269.SZ)
DigiTimes本文为6天前(10/13董事会、10/14公告)旧闻的英文综述,无新增事实且中文媒体已广泛扩散;华大九天仅参股,1.5亿元现金对约500亿市值无短线弹性,标的亚科鸿禹持续亏损、商业化不确定;10月9/12日已两轮放量抢跑、公告当日反跌,明牌利好price-in,无正期望,不做。
展开详情(成交明细 / 研究档案 / 原文全文 / 决策记录链)

研究档案

结论摘要

这是6天前华大九天公告的旧闻被DigiTimes英文重述,无新增信息;直接上市主体仅参股、出资1.5亿相对约500亿市值微不足道,标的尚亏损,且10月9/12日已两轮抢跑,不具备短线edge,回避。

🔎 新鲜度:最早出现 2026-10-13 · 扩散 high · price-in 风险 high ↗ ↗ ↗

消息传播链

  1. 2026-10-13首发巨潮资讯/公司董事会决议公告一手源原文 ↗
    华大九天第二届董事会第二十九次会议10月13日召开,审议相关增资及重组事项,为最早法定披露
  2. 2026-10-14官方披露/报纸刊登中国证券报一手源原文 ↗
    正式关联交易公告:以自有资金及思尔芯股权发起/增资相关合伙企业,深化EDA投资布局
  3. 2026-10-19 14:17 CST财经媒体扩散新浪财经(看点资讯)非一手原文 ↗
    中文媒体明确:1.5亿元+思尔芯7.78%股权对亚科鸿禹增资并推动与思尔芯合并重组,说明DigiTimes文前已广泛传播
  4. 2026-10-20 11:57 CST行业媒体英文综述DigiTimes非一手原文 ↗
    本条信号来源,为已披露事件的英文付费综述,无新增事实

关键理由

  • 若硬做方向,唯一可交易腿是华大九天(301269.SZ):补强硬件仿真/原型验证数字前端EDA,国产替代长线逻辑成立
  • 但本次为参股公司层面的早期整合,1.5亿现金+7.78%参股股权注入,对约500亿市值无短线业绩弹性

主要风险

  • 事件已于10月13-14日由董事会决议/公告披露并被中证报、新浪等转载,本文为6天后英文综述,属明牌旧闻
  • 亚科鸿禹2025净亏5161万、2026H1净亏3556万且硬件仿真器仍在研发,存在整合与商业化不及预期风险

反向证据

  • 做多前查反向 · 来源 web · 日期 2026-10-19 · 影响 weakens
    亚科鸿禹2025收入7135万/净亏5161万,2026H1收入1169万/净亏3556万、净资产下降,硬件仿真器研发周期长、验证与商业化不确定,整合标的基本面弱
    检索:亚科鸿禹 亏损 净亏 硬件仿真器 商业化 风险 原文 ↗
  • 做多前查反向 · 来源 filing · 日期 2026-10-13 · 影响 weakens
    行情显示公告前10月9日+7.96%、10月12日+6.12%两轮放量上涨,近20日累计+12.58%,明牌前已抢跑,公告当日(10-14)反跌-2.07%
    检索:华大九天 思尔芯 亚科鸿禹 公告 股价 抢跑 原文 ↗

先例如何影响了这次决策

对本次决策的影响:因事件为无增量旧闻(STALE)且materiality不足,在量化历史先例之前即可判定无正期望,故未构造先例面板;不引入低质量样本

工具执行结果 · 成功 4 · 降级 0 · 失败 0 · 取消 0
  1. search_processed_events 成功 stock_tools HTTP · 11 ms
    {"result": "search_processed_events:agent query=`empyrean s2c hypersilicon merger hardware emulation | s2c hypersilicon 合并 eda 硬件仿真 | 华大九天 s2c 思尔芯 合并 重组 1.5亿`;结构化索引覆盖完整 72 小时;旧记录兼容扫描近 0.0/72 小时、0 条本臂决策(完整),返回 0 条候选。未命中只表示这些 agent query 表达式没有召回候选,不能据此证明消息首发或不是重复;按当前事件继续正常研判。"}
  2. normalize_ticker 成功 stock_tools HTTP · 6 ms
    {
  3. stock_quote 成功 stock_tools HTTP · 272 ms
    {
  4. web_search 成功 doubao_search · 1,134 ms
    豆包搜索结果(原始查询:华大九天 思尔芯 S2C 合并 重组 1.5亿 公告 10月14日;API SearchType:web)

原文全文

展开原文 · 4,687 字
China's electronic design automation (EDA) industry is consolidating, with Shanghai-based S2C and Wuxi-based HyperSilicon merging into a unified digital front-end EDA platform. Backed by Empyrean Technology and other investors, the deal aims to strengthen domestic capabilities in hardware emulation, chip verification, and simulation.

The merger agreement, announced on October 14, 2026, will bring CNY518.15 million (approx. US$77.6 million) in new investment to support R&D, engineering expansion, customer services, and commercialization of advanced verification tools.
The deal targets hardware-assisted verification, increasingly critical as chip complexity grows. Hardware emulation enables detailed debugging of large-scale designs, while FPGA-based prototyping supports software and firmware development at near-silicon speeds.
By integrating these technologies, the companies aim to establish a unified workflow spanning architecture design, software simulation, hardware emulation, prototyping, and digital debugging, reducing duplicated R&D and accelerating chip verification.
Empyrean-backed merger strengthens China's EDA capabilities
The S2C–HyperSilicon merger represents a broader effort to consolidate China's fragmented digital front-end EDA capabilities, particularly in hardware emulation, a critical technology for verifying increasingly complex chip designs.
According to Empyrean Technology's regulatory filing, the company will invest CNY150 million in cash alongside its existing stake in S2C to support the restructuring. The transaction follows Empyrean's initial investment in S2C in December 2025 and advances its strategy to address gaps in its digital EDA portfolio.
While Empyrean has largely established its core digital circuit design tools, hardware-assisted verification remains an area requiring substantial R&D investment. Combining S2C and HyperSilicon is intended to concentrate technical expertise, eliminate overlapping development efforts, and accelerate the commercialization of domestically developed verification technologies.
The restructuring will also draw support from the Greater Bay Area Fund and a central state-owned enterprise strategic emerging industries fund, providing additional financial resources for long-term development.
Hardware emulation takes center stage
S2C, founded in 2004, has developed a digital front-end EDA portfolio covering architecture design, software simulation, hardware emulation, prototyping, digital debugging, and cloud-based EDA services. Its products serve more than 600 companies across AI, high-performance computing, telecommunications, and automotive electronics.
HyperSilicon, established in 2009, specializes in functional verification, with eight generations of prototyping products and two generations of hardware emulators, including the VeriTiger and HyperSemu product lines. It has served more than 600 users worldwide.
The merger brings together their complementary capabilities to address one of China's key digital EDA development gaps: advanced hardware emulation for large-scale chip designs.
According to the companies' October 14 announcement, the combined platform will leverage more than 800 customers' application scenarios to refine verification tools, shorten development cycles, and accelerate commercialization.
Beyond consolidating product portfolios, the companies aim to integrate previously separate tools into a unified workflow, spanning architecture design, simulation, hardware emulation, prototyping, and system-level verification.
The objective is to reduce duplicated R&D investment while improving interoperability, engineering efficiency, and customer support, strengthening the competitiveness of China's domestic digital front-end EDA ecosystem.
Commercialization risks remain
HyperSilicon faces financial pressure and uncertainty over commercializing its core hardware emulation technology. Revenue reached CNY71.35 million in 2025, with a net loss of CNY51.61 million. In the first half of 2026, revenue was CNY11.69 million, while its net loss reached CNY35.56 million and net assets declined.
Empyrean cautioned that HyperSilicon's hardware emulator remains under intensive development, facing lengthy R&D cycles and uncertainties over product validation and commercial adoption.
The new funding will support engineering, product development, and market expansion, with the merged company's priority being to turn its combined technical capabilities and customer base into commercially viable verification tools. The deal also advances Empyrean's efforts to complete its digital front-end EDA portfolio, particularly in hardware emulation acceleration.

决策记录链 · 只追加

每次领取产生一条记录,重新决策追加一条并以 supersedes 指向被替代的记录(ADR 0014)。

  1. 0d521e498e · 2026-10-20 12:18 · doubao / doubao-seed-evolving-latest-version · 策略包 658c0c1e2ba5当前