三星据报同意将英伟达定制HBM（NVHBM）基底芯片转交台积电3nm代工，台积电集齐三大存储厂base die订单

Nvidia's custom memory design is shifting control of how high-bandwidth memory (HBM) is built from memory makers to its largest customer, and steering a key part of that work to TSMC. Samsung Electronics, which has made every part of its HBM stacks in-house, has agreed after an internal review to use TSMC's 3nm process for the base die of NVHBM, Nvidia's next-generation custom HBM, the Seoul Economic Daily reported on October 18, citing industry sources. The newspaper said it would be the first time the two companies have worked together at the HBM manufacturing stage.

Samsung gives up its turnkey model for Nvidia
An HBM stack consists of DRAM core dies, which serve as the memory, piled on a base die, a logic chip that sits beneath them. Until now, Samsung has produced both for all the HBM it supplies.
The concession is limited. Samsung plans to keep that turnkey approach for standard HBM and for custom HBM supplied to other customers, including AMD, the Seoul Economic Daily said.
The shift had been flagged earlier. ZDNet , citing industry sources, reported that Samsung was rethinking its in-house base die strategy under a dual-track approach in which its core dies could be paired with base dies from Samsung Foundry or TSMC, depending on customer requirements, TrendForce said in early October. For TSMC-made base dies, Samsung's memory business is expected to handle chip design and optimization support, ZDNet reported.
Nvidia writes the specification
According to the Seoul Economic Daily , Nvidia asked Samsung, SK Hynix, and Micron Technology to make the NVHBM base die on TSMC's 3nm process and to standardize the core die on the sixth-generation DRAM process known as 1c. The newspaper said differing manufacturing methods across suppliers make it difficult to deliver consistent performance from a single design and that standardization also reduces the burden of validating each supplier's products separately.
The request follows from the design itself. Nvidia unveiled NVHBM in August, moving the memory controller and the physical interface, or PHY, off the accelerator and into the HBM base die, Network World reported. Nvidia claims up to 30% more memory bandwidth than standard HBM4E, up to 15% lower HBM power consumption, up to 25% more area on the compute die, and up to 67% less PHY and supporting interface area.
Nvidia is also positioning the design beyond its own chips. In a blog post, the company said it "is establishing a standard NVHBM implementation, available from multiple memory providers." The product is aimed at hyperscalers and AI companies developing their own custom accelerators, and Amazon's Annapurna Labs will be the first announced partner to work with Nvidia on the technology, the outlet said.
The memory makers say the arrangement can still pay. Manish Bhatia, Micron's chief operating officer, said HBM is already a premium product category, "but NVHBM adds customized features that create even greater value," The Elec reported. Scott J. DeBoer, Micron's president and chief technology and products officer, said Micron would maintain its advantages in power efficiency, optimized speed performance, and operating margin even with a base die made by an external foundry.
TSMC gathers base die work from all three
If the report holds, all three suppliers would source NVHBM base dies from TSMC. SK Hynix already uses TSMC's 12nm logic process for its HBM4 base die, while TSMC is prioritizing its 3nm process for HBM4E and future custom HBM products, according to EDAILY . At Micron's fiscal fourth-quarter 2026 earnings event on September 30, DeBoer said both NVHBM and the JEDEC-standard HBM4E family are being developed with base dies made using a foundry process, unlike Micron's HBM4, which used an in-house base die. DeBoer did not name the foundry; The Elec reported that Micron is outsourcing the HBM4E base die to TSMC.
Manufacturing maturity helps explain the choice. In a follow-up report, the Seoul Economic Daily said the industry estimates TSMC's 3nm yield at 90% or higher, against about 60% for Samsung Foundry's comparable 2nm SF2 process.
TSMC is also adding 3nm capacity. C.C. Wei, the company's chairman, said on October 15 that nearly 20 fab projects are underway worldwide, including three new 3nm fabs, Taiwan's Central News Agency reported. A 3nm fab in Tainan is expected to begin mass production in the first half of 2027, and another 3nm fab is planned in Tainan, he said.
Capacity is the swing factor
Samsung has kept a fallback. "Samsung is validating whether it can also make the NVHBM base die at its own foundry," an industry official told the Seoul Economic Daily. "This is a hedge in case NVHBM demand exceeds TSMC's production capacity."
Some market watchers see an opening in that hedge. Jukan, an analyst at Citrini, views Samsung as the best placed of the three memory makers to serve Nvidia demand beyond available NVHBM capacity because TSMC must simultaneously budget wafer capacity for Nvidia's Rubin and Rubin Ultra, according to ad-hoc-news. The outlet described this as a potential opening, not a signed order book.