📰 DigiTimesDigiTimesDoubao · 实盘不做把握 7/10不做原因:已被定价
北京时间·🕒 发布 09:36:53·⟳ 抓取 10:02:09 +25m16s·⚡ 决策 10-22 10:04:31 +2m22s·5.6 天前
DigiTimes综述澜起Q3净利翻倍及得一微CXL布局,核心业绩预告已于10月20日官方披露
本文唯一有量级的催化(澜起Q3净利翻倍)是10月20日公司官方业绩预告的旧闻,两个交易日已被重定价约8%且当日盘中回落;得一微CXL仅为未上市、未量产的研发布局,无可交易资产和增量事实,不具正期望入场点。
📄 原文DigiTimes↗ 原文
China's IC designers expand into AI server memory interconnects beyond DDR5
China's IC designers are expanding into high-speed interconnect technologies as AI inference and agent applications fue…
不做 澜起科技(688008.SH)
PRICE_IN:核心利好为10月20日官方业绩预告,DigiTimes 10月22日文章无增量事实;股价两个交易日已累计上涨约7.9%,当日盘中转跌0.87%,旧闻二次扩散阶段追入无edge。
不做 得一微电子(Techwinsemi)(N/A)
NO_TRADABLE_ASSET:公司未上市,H9560 CXL控制器尚在研发、目标2026年底回片验证,无收入、无可交易证券;德明利等同主题映射未经本事件一手证据坐实。
展开详情(成交明细 / 研究档案 / 原文全文 / 决策记录链)
研究档案
结论摘要
DigiTimes这篇是对10月20日澜起科技官方Q3业绩预告的延迟综述,澜起两日已涨约7.9%、今日转跌,新增事实为零;得一微未上市且CXL芯片尚在回片前阶段,故回避。
🔎 新鲜度:最早出现 2026-10-20 · 扩散 high · price-in 风险 high ↗
消息传播链
- 节点
关键理由
- 澜起Q3归母净利12-13亿元、同比+154%~175%基本面确实强劲,但该信息10月20日已由公司官方披露,非本文新增edge
主要风险
- 业绩为未经审计预告,正式财报若不及指引上限或Q4需求指引转弱,前期抢跑资金可能兑现
- 若后续证实得一微H9560与A股公司(如德明利)存在实质供货/合作关系,可能产生独立CXL题材催化,需另行研判
反向证据
- 做多前查反向 · 来源 web · 日期 2026-10-21 · 影响 invalidates
行情显示业绩预告后10/20+2.43%、10/21+5.36%,两日累计约+7.9%,10/22盘中-0.87%回落,催化已price-in且资金开始兑现
检索:澜起科技 688008 10月20日 业绩预告 股价 反应 原文 ↗
先例如何影响了这次决策
对本次决策的影响:确认回避:旧闻二次扩散阶段追入风险收益比差
方向:不适用:结论基于催化陈旧且已重定价(AVOID),无需以历史先例校准涨幅
涨幅量级:无ENTER标的,不校准tp/sl
形态:盘后明牌业绩预告后次日高开/冲高回落的一般性风险与本次两日累计+7.9%后转跌一致,支持不追
工具执行结果 · 成功 4 · 降级 0 · 失败 0 · 取消 0
- search_processed_events 成功 stock_tools HTTP · 5,511 ms
{"result": "search_processed_events:agent query=`montage technology q3 2026 profit preliminary earnings ddr5 rcd | 得一微 techwinsemi cxl h9560 内存扩展控制器 | 澜起科技 2026 三季度业绩预告 ddr5 净利润翻倍`;结构化索引覆盖完整 72 小时;旧记录兼容扫描近 72.0/72 小时、27778 条本臂决策(完整),返回 0 条候选。未命中只表示这些 agent query 表达式没有召回候选,不能据此证明消息首发或不是重复;按当前事件继续正常研判 - normalize_ticker 成功 stock_tools HTTP · 11 ms
{ - stock_quote 成功 stock_tools HTTP · 96 ms
{ - web_search 成功 doubao_search · 1,537 ms
豆包搜索结果(原始查询:得一微 Techwinsemi 上市 CXL 控制器 H9560;API SearchType:web)
原文全文
展开原文 · 3,489 字
China's IC designers are expanding into high-speed interconnect technologies as AI inference and agent applications fuel demand for server CPUs, memory modules and connectivity chips. Montage Technology expects third-quarter 2026 profit to more than double on stronger DDR5 shipments, while Shenzhen-based Techwinsemi is developing Compute Express Link (CXL) memory expansion controllers. Together, these efforts highlight China's growing interest in AI server connectivity.
DDR5 upgrades lift Montage's profit and margins
In a preliminary earnings announcement on October 20, Montage forecast third-quarter revenue of CNY2.079 billion (≈ US$311.3 million), up 46% year-on-year and 10.9% sequentially. Net profit attributable to shareholders is expected to reach CNY1.2 billion to CNY1.3 billion, up 153.6% to 174.7% year-on-year and 4.3% to 13% quarter-on-quarter.
Excluding non-recurring items, profit is projected at CNY950 million to CNY1.05 billion, up 152.6% to 179.2% year-on-year and 32.2% to 46.1% sequentially. In the year-earlier quarter, Montage recorded revenue of CNY1.424 billion, net profit of CNY473 million and adjusted profit of CNY376 million, with basic earnings per share of CNY0.42.
Montage attributed the growth to expanding AI inference and agent workloads, which are lifting server CPU demand and, in turn, shipments of DDR5 memory interface and supporting module chips. Third-, fourth-, and fifth-generation registering clock driver (RCD) chips accounted for a larger share of shipments, improving the company's product mix.
RCD chips buffer and drive clock signals in server memory modules, preserving signal integrity at higher capacities and transfer speeds. Growing adoption of newer-generation DDR5 interfaces is therefore supporting both shipment growth and profitability.
Montage expects interconnect chip revenue of CNY2.047 billion, up 49.3% year-on-year and 20.9% sequentially, accounting for nearly 98.5% of total revenue. Gross margin is projected at 68% to 68.5%, a year-on-year improvement of 2.31pp to 2.81pp. The company anticipates further demand growth in the fourth quarter.
The estimates remain unaudited, with final figures subject to Montage's third-quarter financial report.
Techwinsemi pushes into CXL memory expansion
Beyond DDR5, Techwinsemi is developing its H9560 controller for CXL memory expansion, targeting completion of wafer-return validation by the end of 2026. Its efforts also cover enterprise storage controllers, firmware, solution validation and system compatibility, alongside supply-chain integration and customer adoption.
Built on the PCI Express physical interface, CXL enables high-speed connectivity and resource sharing among CPUs, accelerators and memory devices. Through memory expansion, pooling and sharing, the technology can help data centres allocate capacity more flexibly and improve utilisation for demanding AI workloads.
While Montage focuses on DDR5 memory interfaces and interconnect chips, Techwinsemi is pursuing storage controllers and CXL expansion solutions. Their respective strategies reflect the growing importance of memory capacity, bandwidth and system integration as AI workloads increasingly shift towards inference and autonomous agents.
For Chinese IC designers, high-speed interconnects are becoming an increasingly important part of AI infrastructure, linking advances in memory performance with the need for tighter coordination among server CPUs, accelerators and storage systems.
DDR5 upgrades lift Montage's profit and margins
In a preliminary earnings announcement on October 20, Montage forecast third-quarter revenue of CNY2.079 billion (≈ US$311.3 million), up 46% year-on-year and 10.9% sequentially. Net profit attributable to shareholders is expected to reach CNY1.2 billion to CNY1.3 billion, up 153.6% to 174.7% year-on-year and 4.3% to 13% quarter-on-quarter.
Excluding non-recurring items, profit is projected at CNY950 million to CNY1.05 billion, up 152.6% to 179.2% year-on-year and 32.2% to 46.1% sequentially. In the year-earlier quarter, Montage recorded revenue of CNY1.424 billion, net profit of CNY473 million and adjusted profit of CNY376 million, with basic earnings per share of CNY0.42.
Montage attributed the growth to expanding AI inference and agent workloads, which are lifting server CPU demand and, in turn, shipments of DDR5 memory interface and supporting module chips. Third-, fourth-, and fifth-generation registering clock driver (RCD) chips accounted for a larger share of shipments, improving the company's product mix.
RCD chips buffer and drive clock signals in server memory modules, preserving signal integrity at higher capacities and transfer speeds. Growing adoption of newer-generation DDR5 interfaces is therefore supporting both shipment growth and profitability.
Montage expects interconnect chip revenue of CNY2.047 billion, up 49.3% year-on-year and 20.9% sequentially, accounting for nearly 98.5% of total revenue. Gross margin is projected at 68% to 68.5%, a year-on-year improvement of 2.31pp to 2.81pp. The company anticipates further demand growth in the fourth quarter.
The estimates remain unaudited, with final figures subject to Montage's third-quarter financial report.
Techwinsemi pushes into CXL memory expansion
Beyond DDR5, Techwinsemi is developing its H9560 controller for CXL memory expansion, targeting completion of wafer-return validation by the end of 2026. Its efforts also cover enterprise storage controllers, firmware, solution validation and system compatibility, alongside supply-chain integration and customer adoption.
Built on the PCI Express physical interface, CXL enables high-speed connectivity and resource sharing among CPUs, accelerators and memory devices. Through memory expansion, pooling and sharing, the technology can help data centres allocate capacity more flexibly and improve utilisation for demanding AI workloads.
While Montage focuses on DDR5 memory interfaces and interconnect chips, Techwinsemi is pursuing storage controllers and CXL expansion solutions. Their respective strategies reflect the growing importance of memory capacity, bandwidth and system integration as AI workloads increasingly shift towards inference and autonomous agents.
For Chinese IC designers, high-speed interconnects are becoming an increasingly important part of AI infrastructure, linking advances in memory performance with the need for tighter coordination among server CPUs, accelerators and storage systems.
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