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Nvidia reportedly drives testing interface capacity crunch, pushes Taiwan suppliers

Monica Chen
, Taipei

Sep 10, 2026, 10:46

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Credit: DIGTIMES

AI chip demand is tightening high-end testing interface capacity, and supply-chain sources say Nvidia has raised prices to secure most of the probe card and test socket output from major testing interface vendors. The squeeze is also pushing Taiwan foundry leader TSMC and related IC design customers to assess diversified supply channels for early-stage R&D validation.

According to the sources, testing and analysis companies are not following the traditional high-volume manufacturing route in testing interfaces. Instead, after customers specify special requirements during the R&D stage, these firms handle interface routing design or co-development and then outsource production to third-party foundries. Some of their core capabilities focus on in-house socket production or special contact components, followed by electrical and reliability validation in labs.
Industry sources said their existing small-volume engineering substrate services are the basis for this push into testing interfaces. After IC design companies enter the EVT and DVT engineering validation stages, they typically need only a small number of engineering substrates. However, traditional substrate makers mainly target large production orders, making demand for 5 to 100 units difficult to secure, which often stretches lead times and delays R&D schedules.
Advanced packaging has further raised the difficulty of engineering validation. Architectures such as CoWoS, chiplet, and multi-chip integration combine multiple chips into a single package. If R&D teams need to validate a single die, they still have to design separate engineering substrates and testing interfaces. As a result, testing and analysis vendors are extending engineering substrate services into the design and assembly of sockets, evaluation boards, load boards and burn-in boards.
At present, specialist testing interface makers such as WinWay, MPI and CHPT remain the dominant players in the probe card and mass-production socket markets. By contrast, testing and analysis firms such as iST, MAtek and MSScorps are reportedly targeting niche openings in engineering substrates, R&D-oriented testing interface design and laboratory validation.
Taiwan testing and analysis firms including iST, MSScorps and MAtek have also been moving into new areas in recent years.
MSScorps has expanded its materials analysis (MA) and failure analysis (FA) technologies into MOR materials analysis for High-NA EUV, atom probe tomography, or APT, and SiPh measurement, while also deploying MSS HG equipment and negotiating international cooperative patent licensing. Its revenue model has broadened from analysis services into equipment, co-development, and technology licensing.
MAtek, meanwhile, has adjusted its overseas footprint by selling an 80% stake in its Shanghai subsidiary, will launch Japan's first FA lab in September 2026, and plans to provide FA and MA services in the US in 2027.
As AI chips and advanced packaging continue to raise validation difficulty, competition among vendors is also widening from a single analysis service into full-process support spanning materials, packaging, electrical, optical, and testing.

Article
translated by Charlene Chen and edited by Jack Wu

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