📰 DigiTimes 实时DigiTimes RealtimeDoubao · 实盘不做把握 3/10不做原因:消息已过时
北京时间·🕒 发布 09-07 10:52:00时区推断·⟳ 抓取 09-07 11:02:56·⚡ 决策 09-15 13:16:57 +8d02h·42.2 天前
北方华创64层3D DRAM选择性刻蚀工艺见刊，或为长鑫存储提供EUV之外的路径
消息为8天前(2026-09-07)的旧报道，且本质是实验室论文成果而非可量化订单或量产进展；发布当日北方华创已上涨3.52%消化，随后6个交易日累计回吐，事件窗口和edge均已消失。
📄 原文DigiTimes Realtime↗ 原文
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不做 北方华创科技集团（002371.SZ）
8天前旧报道且为IEEE论文级实验室成果，无量产/订单/CXMT采用事实；发布日已+3.52%反应、随后6日连跌回吐，事件edge已消失，无正期望入场点。
展开详情(成交明细 / 研究档案 / 原文全文 / 决策记录链)
研究档案
结论摘要
北方华创64层3D DRAM选择性刻蚀仅是IEEE论文级实验室验证，未证明量产或CXMT采用，无收入增量；报道距今8天、发布日已上涨3.52%后回落，属已消化的旧软催化，不做。
🔎 新鲜度:最早出现 2026-09-07 · 扩散 medium · price-in 风险 high ↗
关键理由
- 刻蚀工艺若未来量产并被CXMT采用，长期利好国产3D DRAM设备生态，但当前无任何商业兑现节点
- 002371.SZ是唯一直接可交易标的，CXMT未上市
主要风险
- 论文成果到可制造3D DRAM存在良率、性能、成本与整合多重不确定性，短期无收入贡献
- 该报道09-07已公开并被当日上涨消化，追入缺乏新增预期差
反向证据
- 做多前查反向 · 来源 web · 影响 weakens
报道原文与可见信息均无CXMT采用、量产或订单事实，仅有实验室参数；事件日脉冲后连续回落，无新增利多支撑
检索:北方华创 3D DRAM 刻蚀 订单 量产 CXMT 采用 公告 原文 ↗
先例如何影响了这次决策
对本次决策的影响:无可靠先例支撑幅度，叠加已过8天且回吐，直接放弃交易，不设ENTER
方向:无可对齐先例；论文级技术突破类软催化在半导体设备龙头上通常仅带来单日脉冲
涨幅量级:缺乏同市场、同相位(论文/实验室成果发布)且首发锚干净的对齐样本，不足以校准tp/sl
形态:本次标的自身价格已呈发布日单日上涨、随后6日连跌回吐的脉冲回落形态
工具执行结果 · 成功 2 · 降级 0 · 失败 0 · 取消 0
- search_processed_events 成功 stock_tools HTTP · 17 ms
{"result": "search_processed_events:agent query=`naura 64-layer 3d dram selective etching cxmt euv | 北方华创 naura 3d dram 选择性刻蚀 64层 sige | 长鑫存储 cxmt 3d dram 刻蚀 北方华创 ieee`；结构化索引覆盖完整 72 小时；旧记录兼容扫描近 0.0/72 小时、0 条本臂决策(完整)，返回 0 条候选。未命中只表示这些 agent query 表达式没有召回候选，不能据此证明消息首发或不是重复；按当前事件继续正常研判。"} - stock_quote 成功 stock_tools HTTP · 362 ms
{
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Naura 3D DRAM etching breakthrough could give CXMT a new path beyond EUV
Levi Li
, DIGITIMES, Taipei
Sep 7, 2026, 10:52
0
Credit: AFP
China's Naura Technology has demonstrated a selective etching process for 64-layer 3D DRAM structures, potentially giving domestic memory makers another route to raise transistor density while access to advanced EUV lithography remains restricted.
The semiconductor equipment maker detailed a two-step cyclic etching process for alternating silicon (Si) and silicon-germanium (SiGe) layers in a recent IEEE journal paper . The technique achieved a SiGe-to-Si etch selectivity above 500:1 and structural uniformity exceeding 95% across 64 alternating layer pairs, addressing a key manufacturing challenge for vertically stacked DRAM.
The development could be relevant to Chinese DRAM maker CXMT if the process can eventually be integrated into commercial production, although the reported results alone do not establish an EUV-free mass-production route.
Credit: IEEE Xplore
3D DRAM shifts scaling from planar to vertical
3D DRAM moves density scaling from horizontal shrinkage toward vertically stacked transistor structures, broadly following NAND flash's earlier transition to 3D architectures.
For China, that route is especially relevant. Restrictions on EUV lithography and the growing complexity of DUV-based scaling make vertical integration a potential path for reducing reliance on increasingly fine planar patterning, according to Mydrivers and Ijiwei .
Naura's process targets a 64-layer stack of alternating silicon and silicon-germanium films. The SiGe layers must be selectively removed while preserving silicon, creating spaces for structures including word lines, bit lines, and gates.
Credit: Ifeng
Naura targets a critical 3D DRAM etching hurdle
Selective lateral etching is difficult in high-aspect-ratio 3D structures. Poor selectivity can damage the silicon framework, while byproducts deep in the stack can restrict gas flow and create uneven etching.
Naura uses a repeating two-step process. Electrically neutral fluorine radicals first remove SiGe selectively while forming a protective germanium-fluoride-rich layer on silicon. A second step clears reaction byproducts to restore gas transport before the cycle repeats.
Naura reports SiGe-to-Si selectivity above 500:1, with silicon loss below 10 angstroms, or 1 nanometer, per cycle in a 200nm interlayer structure. Structural uniformity exceeds 95% across 64 alternating layer pairs, supporting more consistent etching deep into the stack.
CXMT could gain another path beyond planar scaling
Naura's results could strengthen China's domestic process-tool ecosystem for next-generation DRAM. If CXMT eventually integrates the etching technology, vertical scaling could offer another way to raise memory density without relying exclusively on leading-edge lithography.
Selective etching, however, is only one part of a complex 3D DRAM process, and the paper does not show that CXMT has adopted the technology or reached mass production.
The broader significance is strategic: memory scaling is increasingly shifting from finer lithography toward architecture, materials and process integration. The next test is whether Naura's 64-layer results can translate into manufacturable 3D DRAM with competitive yield, performance and cost.
Article
edited by Jerry Chen
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REALTIME NEWS
Corning sees CPO and glass core as new semiconductor battlegrounds
Tomorrow's Headlines
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Sep 14, 18:46
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Home
Tech
Semiconductors
Naura 3D DRAM etching breakthrough could give CXMT a new path beyond EUV
Levi Li
, DIGITIMES, Taipei
Sep 7, 2026, 10:52
0
Credit: AFP
China's Naura Technology has demonstrated a selective etching process for 64-layer 3D DRAM structures, potentially giving domestic memory makers another route to raise transistor density while access to advanced EUV lithography remains restricted.
The semiconductor equipment maker detailed a two-step cyclic etching process for alternating silicon (Si) and silicon-germanium (SiGe) layers in a recent IEEE journal paper . The technique achieved a SiGe-to-Si etch selectivity above 500:1 and structural uniformity exceeding 95% across 64 alternating layer pairs, addressing a key manufacturing challenge for vertically stacked DRAM.
The development could be relevant to Chinese DRAM maker CXMT if the process can eventually be integrated into commercial production, although the reported results alone do not establish an EUV-free mass-production route.
Credit: IEEE Xplore
3D DRAM shifts scaling from planar to vertical
3D DRAM moves density scaling from horizontal shrinkage toward vertically stacked transistor structures, broadly following NAND flash's earlier transition to 3D architectures.
For China, that route is especially relevant. Restrictions on EUV lithography and the growing complexity of DUV-based scaling make vertical integration a potential path for reducing reliance on increasingly fine planar patterning, according to Mydrivers and Ijiwei .
Naura's process targets a 64-layer stack of alternating silicon and silicon-germanium films. The SiGe layers must be selectively removed while preserving silicon, creating spaces for structures including word lines, bit lines, and gates.
Credit: Ifeng
Naura targets a critical 3D DRAM etching hurdle
Selective lateral etching is difficult in high-aspect-ratio 3D structures. Poor selectivity can damage the silicon framework, while byproducts deep in the stack can restrict gas flow and create uneven etching.
Naura uses a repeating two-step process. Electrically neutral fluorine radicals first remove SiGe selectively while forming a protective germanium-fluoride-rich layer on silicon. A second step clears reaction byproducts to restore gas transport before the cycle repeats.
Naura reports SiGe-to-Si selectivity above 500:1, with silicon loss below 10 angstroms, or 1 nanometer, per cycle in a 200nm interlayer structure. Structural uniformity exceeds 95% across 64 alternating layer pairs, supporting more consistent etching deep into the stack.
CXMT could gain another path beyond planar scaling
Naura's results could strengthen China's domestic process-tool ecosystem for next-generation DRAM. If CXMT eventually integrates the etching technology, vertical scaling could offer another way to raise memory density without relying exclusively on leading-edge lithography.
Selective etching, however, is only one part of a complex 3D DRAM process, and the paper does not show that CXMT has adopted the technology or reached mass production.
The broader significance is strategic: memory scaling is increasingly shifting from finer lithography toward architecture, materials and process integration. The next test is whether Naura's 64-layer results can translate into manufacturable 3D DRAM with competitive yield, performance and cost.
Article
edited by Jerry Chen
AI Search
Related stories
DRAM scaling hits limits as next-generation memory faces delays
Commentary: YMTC's 3D DRAM push challenges CXMT and global memory leaders
Samsung and SK Hynix reportedly accelerate VCT DRAM development as stepping stone to 3D DRAM
DRAM process development direction: 3D DRAM
DRAM process development challenges: DRAM structure in process miniaturization
Show more
Categories
Chips + components IC manufacturing Memory chips
Tags
3D China CXMT DRAM EUV IEEE Naura Technology silicon transistor
Share this article
Other links
Related topics
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Regions
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