Synopsys 在 Semiconductor Engineering 发布赞助白皮书，宣传其面向 Intel 18A(RibbonFET/PowerVia)的嵌入式存储 IP，无订单/业绩等可交易新增事实

Low Power-High Performance >
Breaking The Memory Bottleneck In AI And HPC SoCs
Low Power-High Performance

WHITEPAPERS

Opimizing embedded memory IP for RibbonFET and PowerVia.
October 19th, 2026 -
By: Synopsys

Embedded memory, not compute, has become the limiting factor in AI and HPC SoCs, consuming more than half of total die area while constraining bandwidth, latency, and energy efficiency. As the industry transitions to gate-all-around (GAA) devices and backside power delivery network (BSPDN) technology, embedded memory architectures must evolve to keep pace.
This white paper examines how these shifts redefine embedded memory requirements and how Synopsys Embedded Memory IP addresses them through device-aware architectures, power-optimized designs, and highly configurable compilers. It also presents silicon results from SRAM and Register File test chips on the Intel 18A process node, including density improvements in the 5–10% range and ISO-power performance gains of up to approximately 4%.
Read the paper to discover how RibbonFET and PowerVia enable PPA improvements and reduce advanced-node integration risk.
What you’ll learn:
- Why embedded memory, not compute, is limiting AI and HPC SoC performance
- How GAA devices and BSPDN technology reshape advanced-node embedded memory
- The critical PPA, power-delivery, and configurability requirements for embedded memory IP
- How RibbonFET and PowerVia enable measurable PPA improvements
- What silicon-proven SRAM and Register File results show on Intel 18A
To read more, click here.
- Nanoelectromechanical Switches Target More Efficient Embedded DRAM (UC Berkeley, Samsung, Intel) October 18, 2026 by Technical Paper Link
- A Composable Thermal Solver For Heterogeneous 2.5D/3D-IC Packages (Cadence, Notre Dame) October 18, 2026 by Technical Paper Link
- Thermal Side Channels Create New Security Risks For Autonomous Vehicles (Missouri S&T) October 18, 2026 by Technical Paper Link
- Characterization of HBM Power Consumption (ETH Zurich, NYU) October 14, 2026 by Technical Paper Link
- Simulations Pinpoint Leakage Pathway In GAAFETs (Sandia, Luxembourg) October 14, 2026 by Technical Paper Link
As AI clusters push beyond rack-scale limits, optical interconnects and circuit switching are reshaping how data centers scale.

by Bryon Moyer

Is it better to cram more compute into each rack or rethink the architecture?

The next power bottleneck is no longer just inside the accelerator — it is the full conversion path from medium-voltage AC to sub-1V silicon.

by Liz Allan

As the semiconductor ecosystem pivots to AI, it is transforming how IP is created, verified, managed, and sold.

No system can be optimized without an understanding of both the hardware and software, and making the right architectural choice requires cooperation.

by Brian Bailey

Power, token cost, interconnects, and software orchestration are pushing data centers toward heterogeneous clusters built from CPUs, GPUs, NPUs, optics, and custom accelerators.

For compute-intensive applications, clusters of nodes that act as a single computer offer a way to scale performance and provide a workaround for organizations that lack access to leading-edge AI chips.

Redundant feeds protect uptime, but they also strand capacity that could support more hardware.

-
Newsletter Signup
2.5D
5G
advanced packaging
AI
AMD
ANSYS
Apple
Applied Materials
ARM
Arteris
automotive
business
Cadence
chiplets
DRAM
EDA
EUV
GlobalFoundries
Google
IBM
imec
Infineon
Intel
IoT
IP
Keysight
Lam Research
machine learning
memory
Mentor
Mentor Graphics
MIT
Nvidia
NXP
Qualcomm
Rambus
Samsung
security
SEMI
Siemens
Siemens EDA
Synopsys
test
TSMC
verification
- RISHI BHOOSHAN on Low-Temp Solders Are Suddenly Critical For Chiplets And Photonics
- brian piercy on Photonics Fundamentals For Electronics Engineers: eBook
- NEGA on Artificial Intelligence For Industrial Applications
- Erictc on Advanced Packaging Fundamentals for Semiconductor Engineers: eBook
- Oliver Li on Photonics Fundamentals For Electronics Engineers: eBook
- Ron Lavallee on Intuition and AI
- Liz Allan on Multi-Agent AI Systems Must Work Like An Orchestra Without A Conductor
- Simon Davidmann on Multi-Agent AI Systems Must Work Like An Orchestra Without A Conductor
- Ben Zaryouh on Redefining Processes At Sub-2nm
- Loma Harvey on Chip Industry Technical Paper Roundup: Sept. 8
- Ron Lavallee on From Spec To Formal Properties
- delli on Chip Security Moves From Checkbox Compliance To Continuous Defense
- mark holdaway on From Spec To Formal Properties
- Viska Clanella Nugroho on All AI Data Center Interconnects Will Be Optical Within 5 Years
- Tom Katsioulas on AI: Friend And Foe For Chip Security
- Alex @ APIVALE on Chip Industry Week In Review
- Matt bailey on AI Is Rewriting The IP Playbook
- Matt bailey on AI Models Transform Defect Inspection And Review, But Can Fail To Scale
- Alexis R. Ware on Neural Network Model Quantization On Mobile
- Zack63 on Change Is Tough
- Yağız Boz on EDA/SIP Revenue Up 12.7%; APAC Roars Back
- Murugavel Ganesan on Executive Outlook: Agentic AI’s Impact On Chip Design
- F. Chen on Mask Economics Shape High-NA EUV Adoption
- B.S. Deepaksubramanyan on Designing Chips That Can Explain Themselves
- Brian Bailey on Disturbance In Verification
- David Murray on Disturbance In Verification
- Ramesh Narayanaswamy on Disturbance In Verification
- Cliff Greenberg on Research Bits: Jun. 2
- Peter Ateshian on Detect, Diagnose, And Debug Using Sensors And Functional Monitoring
- Dr. Dev Gupta on Chip Industry Week In Review
- Ed Sperling on The Sub-2nm Paradox
- Jan Hoppe on The Sub-2nm Paradox
- Jan Hoppe on Toward Agentic Verification
- Riko R on With Chiplets, What Role Does Economics Play?
- C Lytle on Flash Getting Stacked High-Bandwidth Version
- Saket Goyal on HBM Shifts Testing Left To Preserve AI Chip Yield
- Debamitro Chakraborti on Creating Agentic EDA Methodologies
- Wim Bakker on Batteries Charge To The Edge
- Ron Richter on TSV Complexity Leads To Manufacturing Bottleneck
- François on The Petabyte Problem: How AI Is Finally Making Semiconductor Manufacturing Data Actionable
- Anonymous on The One Bit Problem That Can Break a System
- JC Bouzigues - IROC Technologies on The One Bit Problem That Can Break a System
- Tom Fitzpatrick on All Software Is Hardware-Dependent
- Anonymous on Memory Wall Gets Higher
- Gregory Haley on Detecting Chemical Variability At Advanced Nodes
- Matt Groves on A Framework That Generates Chip Layouts Directly From Natural Language Specifications (U. of Bristol, RAL)
- AICHIPS on How AI Will Impact Chip Design And Designers
- Martijn Fransen on Detecting Chemical Variability At Advanced Nodes
- Narek on Digital Twins: The Cloud’s The Limit
- Freelancer on Chip Industry Talent Shortage Drives Academic Partnerships
- Chris Riches on Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers
- Jon on Robust Dynamic Voltage Droop Mitigation And Power Management
- Ashfaq on Minimum Energy Per Query
- Robert Boissy on Can A Computer Science Student Be Taught To Design Hardware?
- Hank Walker on Can A Computer Science Student Be Taught To Design Hardware?
- fieke khan on Bump Co-Planarity And Inconsistencies Cause Yield, Reliability Issues
- Rajiv on Chip Industry Week in Review
- Guy van der Walt - Thermco on Chiplets And 3D-ICs Add New Electrical And Mechanical Challenges
- Stephen W on Chiplet Fundamentals For Engineers: eBook
- ShrdMem256 on The Verification Conundrum
- Brendan McGuire on Wafer Probe Struggles To Adapt To Multi-Die Assemblies
- NobodyTestedThis on The Verification Conundrum
- Fiber Techs San Francisco on Agentic AI In Chip Manufacturing
- SF Fiber Techs on Oxides Bring Low Leakage Transistors To Leading-Edge Memories
- humic on Addressing Critical Tradeoffs In NPU Design
- Dr. Dev Gupta on Liquid Cooling Gains Traction In Data Centers
- Mikko Utriainen, Chipmetrics on Metrology Digs Deep To Produce Next-Generation 3D NAND
- Raymond Doerr on Wafer Bonding Mechanisms Using SiCN Films For Hybrid Bonding Applications In 3D Integration
- Hoyong Lee on Chiplets Vs. Soft IP: Different In Almost Every Way
- Nano Banana AI on Blog Review: Dec. 17
- JS Paek on Thermal Management In 3D-IC: Modeling Hotspots, Materials, & Cooling Strategies
- Larry K on Chiplets Vs. Soft IP: Different In Almost Every Way
- Seceon.Inc on Resilient And Optimized GenAI Systems
- Linda Christensen on AI With Open And Scaled Data Sharing in IC Manufacturing (NIST)
- komputer on AI With Open And Scaled Data Sharing in IC Manufacturing (NIST)
- Sree on The Thermal Trap: How Dielectrics Limit Device Performance
- David Muncier on China GenAI: Who Will Fill The Vacuum?
- acp on Is There Still a Future for Hard Disk Drives?
- Carlos Borer on Legacy Process Nodes Going Strong
- Raj Sodhi on AI Meets Device Modeling: Transforming Compact Modeling With Machine Learning
- Jaynarayan Tudu on Semiconductor Test Faces Technology Shifts In The AI Era
- Mihai Buta on Why In-Memory Computation Is So Important For Edge AI
- Silver Luis on The Competitive Advantage Of SRAM PUF Technology
- Gretchen Patti on Advanced Packaging: A Key Technology For The Next Generation Of Electronics
- Ev roach on AI Bubble Or Boom?
- Kathleen Murphy-Weber on Chip Industry Week in Review
- Raz on Multi-Die Verification
- Paul C on Scaling Memory With Molybdenum
- JWS on Scaling Memory With Molybdenum
- Klein miller on Electrifying Everything: Power Moves Toward ICs
- Team at Rise Design Automation on What Does Semiconductor Disruption Look Like?
- masa mizuno on Physics Limits Interposer Line Lengths
- Lou Covey on What Does Semiconductor Disruption Look Like?
- Ricardo Shiroma on Complex Mix Of Processors At The Edge
- Cor on Glass Substrates Gain Momentum
- Daya Young on New Antennas And Advanced ICs Needed For 6G
- Subramanian Srikanteswara Iyer on Manufacturing At The Limits
- Doug La Tulipe on Coloring Optical Signals For More Bandwidth In Data Centers
- WH on The Hidden Cost Of Contact Resistance
- Raymond Doerr on Metrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding
- Raymond Doerr on Manufacturing At The Limits
- Mallikarjun on The Evolution of DRAM
- Klein Miller on Democratizing Design: How The CHIPS Act Is Reshaping EDA And Semiconductor Innovation
- Klein Miller on Lessons From 30 Years In The Trenches On The Future Of Semiconductor Manufacturing
- Jonathan Kolber on Preparing For The Quantum Computing Age
- Pramod Gupta on Challenges In Stacking HBM
- Madeline Lueilwitz on Reconfigurable Single-Walled CNT FeFET (Univ. of Pennsylvania, Yonsei et al.)
- Anne Meixner on Need For KGD Drives Singulated Die Screening
- Capt kirk on Designing A Better Clock Network
- Alex Martin on AI Effort And Money Misplaced
- Hamilton Carter on AI Effort And Money Misplaced
- Ilmu Komunikasi on Reconfigurable Single-Walled CNT FeFET (Univ. of Pennsylvania, Yonsei et al.)
- Giovanni Lostumbo on Will New Processor Architectures Raise Energy Efficiency?
- Brendon Berg on ESD Guns, Transients And Testing…Oh My!
- GD on All About Interconnects
- Raimo on Crisis Ahead: Power Consumption In AI Data Centers
- Fred Chen on Laser-Focused Results: Improving EUV Line Edge Roughness With Ion Beam Etching
- Fred Chen on Many Options For EUV Photoresists, No Clear Winner
- Amba Prasad on Advanced Packaging Fundamentals for Semiconductor Engineers: eBook
- Shakir Ullah on The Race To Replace Silicon
Breaking The Memory Bottleneck I... Synopsys
Why Physical AI Is So Hard To En... Brian Bailey