力成宣布全球首座面板级AI芯片封装厂2027年量产，投资超700亿新台币

HSINCHU, Taiwan -- Taiwan's Powertech Technology says it will start production at the world's first panel-level chip packaging facility for AI chips as soon as early 2027 to make server central processing units, artificial intelligence computing chips and advanced optics.
Powertech's schedule, if achieved, would put it ahead of contract chipmaker Taiwan Semiconductor Manufacturing Co. in adopting the next-generation of packaging technology for AI chips.
Chip packaging refers to the technology used to arrange different types of chips onto wafers or substrates. Panel-level packaging -- Powertech's specialty -- involves packaging chips onto a large rectangular panel-like substrate rather than on conventional round wafers. This provides a larger packaging area, which in turn allows more chips with different functions to be integrated into a single package, paving the way for larger and more powerful AI computing systems.
Speaking in Hsinchu on Wednesday, Powertech Chairman D.K. Tsai told Nikkei Asia that the company will invest more than $70 billion New Taiwan dollars ($2.2 billion) through 2027 to establish the production line in the northwestern Taiwanese city.
"It's the biggest bet in my life, and we have worked so long for today," Tsai said.
Powertech was previously best known as the world's largest contract memory chip packaging and testing service provider, counting Micron, Kioxia and SanDisk among its key customers. But it started research and development of advanced panel-level packaging as far back as 2016.
The company's remarks came after it announced a deal with Broadcom, a key AI computing chip developer, to set up a joint venture in Singapore for premium AI chips and advanced packaging. The Singapore plant is slated to start production around 2028.
AMD and Broadcom are among Powertech's top customers for its advanced chip packaging business and are expected to be among the first adopter of the panel-level packaging services, too, according to industry executives familiar with the matter.
TSMC's advanced chip packaging technology, viewed as the gold standard by AI market leaders including Nvidia, Google and Amazon, is still based on round wafers. The chipmaking titan, however, is also developing its own panel-level packaging technology, known in the industry as chip-on-panel-on-substrate, or CoPoS, Nikkei reported earlier.
Powertech, meanwhile, has been pursuing a number of diversification efforts, including expanding into the packaging and testing of a broader range of logic chips through affiliates including Greatek Electronics and Tera Probe. More recently, it acquired an On Semiconductor chip packaging and testing facility in the Philippines to expand its presence in power-management-related chips, a key growth area amid the massive buildout of AI data centers.
Chip packaging was once considered less technologically sophisticated than chip manufacturing but in recent years has become a critical step in producing increasingly powerful AI computing chips. Securing additional advanced packaging capacity has emerged as a key bottleneck in the push to expand AI chip production. Intel, for instance, is working to increase its advanced chip packaging capacity in hopes of winning over more customers to its contract chipmaking business.
TSMC Chairman C.C. Wei earlier said his company welcomes more players entering the advanced chip packaging market to give its customers more options, as TSMC's own packaging capacity remains constrained due to the heavy demand for AI infrastructure.