高通HBC获三星电子与SK海力士协作推进，首代拟随AI250明年商业化出货

Samsung Electronics and SK hynix are actively collaborating with Qualcomm on the commercialization of its High Bandwidth Compute (HBC) technology, while continuing their existing high-bandwidth memory (HBM) development roadmaps.
Durga Malladi, executive vice president and general manager at Qualcomm, said at the Deutsche Bank Technology Conference 2026 on Aug. 26 that he visited Korea and met with the two major memory manufacturers shortly after Qualcomm presented the benefits of HBC and highlighted shortcomings of HBM at its Investor Day. Malladi said he initially expected strong pushback from the two companies over the presentation, but instead they actively proposed collaborating on the HBC project. The two memory makers are now participating in HBC development alongside their HBM roadmaps.
HBC stacks multiple low-power DRAM (LPDDR) chips vertically and places them on top of an accelerator chip, or XPU, which serves as the compute die underneath. The architecture can achieve higher data-transfer bandwidth than conventional systems that connect compute and memory horizontally. It is a form of near-memory computing (NMC) and, like HBM, uses through-silicon vias (TSVs) for vertical stacking.
Qualcomm officially unveiled HBC at its Investor Day in June. Tony Pialis, executive vice president and general manager of the Data Center division at Qualcomm, said at the time that GPUs and HBM constantly exchange data, generating substantial heat and consuming large amounts of power. He argued that the architecture could no longer keep pace with the growth of artificial intelligence (AI) models and required innovation. Qualcomm positioned HBC as an alternative to HBM's structural limitations.
HBC was developed to address bottlenecks in AI inference. Its effective data-transfer bandwidth reaches hundreds of terabytes per second (TB/s). Aggregate HBM bandwidth in recent AI accelerators is around 21 to 24 TB/s. Compared with HBM at the same power consumption, HBC offers six times the bandwidth and six times the token-throughput efficiency. Compared with conventional GPU systems, token throughput can be as much as eight times higher at the same power. It also offers an advantage in total cost of ownership (TCO) compared with SRAM, which is faster than conventional DRAM.
Qualcomm will handle only the design and system-integration roles in HBC manufacturing. It will develop the compute die placed beneath the DRAM chips and provide the TSV design. Memory manufacturers Samsung Electronics and SK hynix will handle DRAM stacking. Qualcomm plans to work with TSMC on the integration and packaging of each technology.
Malladi said first-generation HBC products are scheduled for commercialization and shipments next year, and Qualcomm is working closely with the two Korean memory manufacturers to ensure adequate DRAM supply. He said first-generation HBC has already arrived at Qualcomm's labs for validation, while second-generation HBC will boost compute-die performance further and widen the performance gap with next-generation HBM.
First-generation HBC will be deployed in Qualcomm's AI250 AI accelerator next year. The company plans to launch the AI300 with second-generation HBC in 2028. HBC can also be attached to Qualcomm's Dragonfly C1000 data-center server CPU.
HBC can also be supplied to customers as a standalone product, similar to HBM. Hyperscalers that develop and own their own AI compute chips could purchase HBC separately and integrate it with their processors.
Malladi said HBC is a general-purpose technology and Qualcomm is researching and developing technical specifications suitable for a range of consumer devices, including smartphones, tablets, PCs, extended-reality (XR) devices and automobiles. The company intends to bring HBC to consumer devices for on-device AI processing. Commercialization typically follows about three years after the product-planning and discussion stage.