韩媒称三星将借台积电3nm产线为英伟达定制HBM(NVHBM)生产基底裸片，但核心内容一个月前已报道

Samsung Electronics (005930) has joined hands with its foundry archrival TSMC in developing custom high-bandwidth memory for Nvidia because artificial intelligence chips are running into a memory bottleneck in both performance and supply. With HBM data transfer speeds unable to keep pace with graphics processing unit computing power, the plan is to lift HBM performance using TSMC's advanced logic process while adding TSMC's manufacturing capacity to expand supply.
Nvidia is working with Samsung Electronics and TSMC to custom-design the base die, a core component of its own HBM product called NVHBM, according to industry sources on the 18th. The base die sits at the bottom layer of an HBM stack and consists of logic circuits that control the signals memory chips exchange, determining data transfer speeds. Product competitiveness hinges on how it is designed.
The NVHBM custom base die is distinguished by moving the memory controller from the GPU. Auxiliary functions previously handled by the GPU are shifted to the NVHBM base die, and the freed-up GPU space is filled with additional computing circuits to raise overall performance. To make room for the controller on the base die, the area of the physical layer, the circuitry that exchanges electrical signals with external chips, was reduced by 60% from standard HBM products. As a result, NVHBM can widen memory bandwidth by up to 30% and cut power consumption by 15% compared with standard seventh-generation HBM4E.
Nvidia's requirement that the NVHBM base die use TSMC's 3-nanometer logic process stems from this design approach. Packing functions relocated from the GPU into the base die requires an ultrafine 3-nanometer-class process capable of integrating more circuits into a limited area. Cutting production costs also demands a high yield, or the share of working chips per wafer.
The industry estimates TSMC's 3-nanometer yield at above 90%, compared with roughly 60% for the comparable Samsung Foundry 2-nanometer (SF2) process. For Nvidia, consolidating base die production at TSMC is the more stable choice.
A bigger factor than technical conditions is that HBM supply is failing to keep up with demand. Investment bank UBS forecasts HBM demand next year at about 61.5 billion gigabits, a measure of storage capacity, up 91% from this year. New shipments from memory makers, by contrast, are expected to reach 54.6 billion gigabits, a gain of just 49% over the same period. That implies a supply shortfall of 11% against demand.
Samsung Electronics must raise output of both the core die and the base die, the two main components of HBM, to meet rising demand. The core die, which serves as the memory chip, is produced using the advanced sixth-generation 1c DRAM process at Line 17 of the Hwaseong campus and at P2, P3 and P4 at the Pyeongtaek campus. P5-1, under construction with first operation targeted for the year after next, will also run mainly 1c lines.
Base die capacity, however, is relatively limited. Samsung Electronics' 4-nanometer base die lines are located only at Hwaseong Line 17 and part of Pyeongtaek P3. The current production setup, designed around demand for standard HBM, cannot adequately absorb custom HBM volumes such as NVHBM.
TSMC has the capacity to cover the base die shortfall that Samsung Electronics cannot handle. At its third-quarter earnings announcement on the 15th, TSMC said it would add two new lines to the existing 3-nanometer line at Fab 18 in Tainan, Taiwan, with mass production beginning in the first half of next year and the first half of the year after next, respectively. It also plans 3-nanometer lines at its second plant in Arizona and its second plant in Kumamoto, Japan, targeting mass production in the third quarter of next year and in 2028.
That does not mean base die production is locked in at TSMC. While using TSMC's base die for NVHBM at Nvidia's request, Samsung Electronics is also preparing to produce the component at its own foundry in anticipation of continued demand growth.
An industry official said TSMC's 3-nanometer lines also make high-performance computing and smartphone chips, so allocated volumes could hit a ceiling. Samsung Foundry is therefore validating NVHBM base die production on its 2-nanometer process, which is comparable to TSMC's 3-nanometer technology, the official said.
Another industry expert said the joint development of Nvidia's NVHBM has broadened cooperation between Samsung Electronics and TSMC from advanced packaging into making core HBM components. The two companies, which worked together on TSMC's CoWoS packaging process for AI chips four years ago, joining hands amid a global memory shortage carries significant implications for the industry, the expert said.