📊 TrendForceTrendForceCodex · 实盘不做把握 5/10不做原因:证据不足
北京时间·🕒 发布 07:30:55·⟳ 抓取 07:31:13 +18s·⚡ 决策 09-01 07:32:40 +1m27s·56.4 天前
联发科强化先进封装与硅光布局，台积电封装老将侯尚加入并称将急补人才
这是方向偏正面的产业媒体报道，但核心是人才加入和技术路线强化，没有新增合同、客户、金额、量产或指引，短线交易edge不足。
📄 原文TrendForce↗ 原文
[News] MediaTek Ramps Up Advanced Packaging Push as TSMC Veteran Shang Hou Calls for More Talent
AI chip competition is expanding beyond advanced nodes into advanced packaging and silicon photonics. According to UDN…
不做 联发科（2454.TW）
不做联发科（2454.TW）：事件偏利好但只是人才与技术布局确认，缺少订单、金额、量产和指引增量，短线edge不足。
展开详情(成交明细 / 研究档案 / 原文全文 / 决策记录链)
研究档案
结论摘要
联发科延揽台积电先进封装老将，有助于AI ASIC、CPO、硅光和先进封装能力建设；但该信息更像中长期战略投入信号，缺少可量化业绩增量与确定交付节点，且TrendForce原文为转述UDN、MoneyDJ和工商等报道，不足以支持立即交易。
消息传播链
- TrendForce称侯尚在8月31日SEMICON Taiwan硅光论坛发表先进封装人才与能力建设相关表态；搜索仅命中UDN频道页，未取得完整原文。
- TrendForce将UDN、MoneyDJ、TechNews和工商时报信息整合为联发科强化先进封装与硅光布局的产业报道。
- SEMICON Taiwan日程显示8月31日存在先进封装相关论坛，说明事件发生场景真实，但该页面不确认侯尚表态内容。
关键理由
- 事件验证联发科正把AI ASIC竞争从设计延伸到先进封装、硅光和高速互连协同优化。
- 侯尚和Douglas Yu等台积电封装人才加入，提高联发科承接大规模AI ASIC项目的技术可信度。
- 量级上，现有公开信息只有研发与人才投入，未披露新增销售基数、可触达订单、收入增量或市值占比，因此不能量化短线业绩弹性。
主要风险
- AI ASIC客户、订单金额和量产时间未被本事件确认，若只是能力建设，短线容易被市场视为旧叙事。
- 联发科AI ASIC与先进封装布局已多次被媒体报道，新增信息可能不足以形成明显预期差。
反向证据
- 做多前查反向 · 来源 web · 日期 2026-08-31 · 影响 weakens
可见公开材料更多是合作、技术路线和人才布局，未找到本事件对应的新增订单金额或盈利指引上调。
检索:MediaTek advanced packaging AI ASIC order guidance customer confirmation 2026 原文 ↗ - 做多前查反向 · 来源 web · 日期 2026-08-31 · 影响 weakens
论坛材料确认先进封装行业热度，但无法坐实联发科短期收入或利润增量。
检索:SEMICON Taiwan 2026 advanced packaging MediaTek forum financial impact 原文 ↗
先例如何影响了这次决策
对本次决策的影响:先例不足与事件量级不足共同压低置信度，最终不下单。
方向:没有足够同市场、同机制、同相位的可量化先例支持短线买入。
涨幅量级:本事件缺少订单、金额和指引，无法用历史订单或获客先例校准涨幅。
形态:人才加入和技术路线强化类报道通常更偏叙事确认，若无订单或财务指引，容易出现反应弱或高开回落。
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原文全文
展开原文 · 3,179 字
[News] MediaTek Ramps Up Advanced Packaging Push as TSMC Veteran Shang Hou Calls for More Talent
AI chip competition is expanding beyond advanced nodes into advanced packaging and silicon photonics. According to UDN News, MediaTek has been strengthening its capabilities in these areas, with Shang Hou, who recently joined the company as vice president of advanced packaging after retiring from TSMC, helping lead the effort. Appearing on August 31 at the SEMICON Taiwan 2026 Silicon Photonics International Forum, Hou said his first task at MediaTek is to “urgently strengthen” its advanced packaging capabilities and continue recruiting talent in the field.
Hou’s move has drawn significant industry attention. As the report highlights, he was deeply involved in TSMC’s advanced packaging and silicon photonics development and named the company’s COUPE (Compact Universal Photonic Engine) silicon photonics integration platform. He also worked on TSVs, chip stacking, and 2.5D CoWoS packaging, making him a key veteran of TSMC’s advanced packaging development.
The report notes that Hou’s move reflects MediaTek’s push to strengthen advanced packaging as it expands into AI data centers and large-scale ASICs. As AI chip competition shifts toward the joint optimization of logic chips, HBM, advanced packaging, and high-speed interconnects, technologies such as 2.5D and 3D packaging, CPO, and silicon photonics are requiring IC designers to consider packaging, thermal management, power delivery, and photonic-electronic integration earlier in the design process.
On the technology front, MoneyDJ notes that MediaTek said at its July earnings call that its 448G SerDes development is on track for completion in the second half of 2027. The company is using co-packaged copper (CPC) for high-speed, energy-efficient interconnects, while its next-generation solutions will move toward CPO, with development already underway on TSMC’s COUPE platform. MediaTek is also offering pre-validated subsystems spanning 3.5D platforms, memory, I/O, and high-speed interconnects to shorten time to market and expand its AI ASIC capabilities toward broader system and platform deployment.
MediaTek Deepens Advanced Packaging Push
Hou is not the only TSMC advanced packaging veteran to recently join MediaTek. As noted by TechNews, Douglas Yu, a key advanced packaging R&D veteran and one of TSMC’s so-called “Six R&D Knights,” joined MediaTek in May. Yu played a pivotal role in developing CoWoS and is expected to strengthen MediaTek’s integration of advanced packaging and chip design.
MediaTek is also diversifying its advanced packaging strategy. According to Commercial Times, the company disclosed during its latest earnings call that its AI ASIC projects are using both TSMC’s CoWoS and Intel’s EMIB-T advanced packaging technologies, signaling a more diversified approach to meet the varying requirements of customers developing large-scale AI chips.
Read more
- [News] Marvell, AMD Reportedly Shake Up Google TPU Race, Putting Broadcom, MediaTek Under Pressure
- [News] MediaTek Advances 400G SerDes on 2nm, Targeting Google TPU v10 and Meta AI ASIC Orders
(Photo credit: MediaTek)
AI chip competition is expanding beyond advanced nodes into advanced packaging and silicon photonics. According to UDN News, MediaTek has been strengthening its capabilities in these areas, with Shang Hou, who recently joined the company as vice president of advanced packaging after retiring from TSMC, helping lead the effort. Appearing on August 31 at the SEMICON Taiwan 2026 Silicon Photonics International Forum, Hou said his first task at MediaTek is to “urgently strengthen” its advanced packaging capabilities and continue recruiting talent in the field.
Hou’s move has drawn significant industry attention. As the report highlights, he was deeply involved in TSMC’s advanced packaging and silicon photonics development and named the company’s COUPE (Compact Universal Photonic Engine) silicon photonics integration platform. He also worked on TSVs, chip stacking, and 2.5D CoWoS packaging, making him a key veteran of TSMC’s advanced packaging development.
The report notes that Hou’s move reflects MediaTek’s push to strengthen advanced packaging as it expands into AI data centers and large-scale ASICs. As AI chip competition shifts toward the joint optimization of logic chips, HBM, advanced packaging, and high-speed interconnects, technologies such as 2.5D and 3D packaging, CPO, and silicon photonics are requiring IC designers to consider packaging, thermal management, power delivery, and photonic-electronic integration earlier in the design process.
On the technology front, MoneyDJ notes that MediaTek said at its July earnings call that its 448G SerDes development is on track for completion in the second half of 2027. The company is using co-packaged copper (CPC) for high-speed, energy-efficient interconnects, while its next-generation solutions will move toward CPO, with development already underway on TSMC’s COUPE platform. MediaTek is also offering pre-validated subsystems spanning 3.5D platforms, memory, I/O, and high-speed interconnects to shorten time to market and expand its AI ASIC capabilities toward broader system and platform deployment.
MediaTek Deepens Advanced Packaging Push
Hou is not the only TSMC advanced packaging veteran to recently join MediaTek. As noted by TechNews, Douglas Yu, a key advanced packaging R&D veteran and one of TSMC’s so-called “Six R&D Knights,” joined MediaTek in May. Yu played a pivotal role in developing CoWoS and is expected to strengthen MediaTek’s integration of advanced packaging and chip design.
MediaTek is also diversifying its advanced packaging strategy. According to Commercial Times, the company disclosed during its latest earnings call that its AI ASIC projects are using both TSMC’s CoWoS and Intel’s EMIB-T advanced packaging technologies, signaling a more diversified approach to meet the varying requirements of customers developing large-scale AI chips.
Read more
- [News] Marvell, AMD Reportedly Shake Up Google TPU Race, Putting Broadcom, MediaTek Under Pressure
- [News] MediaTek Advances 400G SerDes on 2nm, Targeting Google TPU v10 and Meta AI ASIC Orders
(Photo credit: MediaTek)
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