📊 TrendForceTrendForceQwen · 实盘不做把握 3/10不做原因:标的无直接敞口
北京时间·🕒 发布 07:30:55·⟳ 抓取 07:31:13 +18s·⚡ 决策 09-01 07:33:07 +1m54s·56.7 天前
联发科前台积电先进封装副总裁侯尚厚在SEMICON Taiwan 2026表示将紧急强化联发科先进封装能力并招募人才
本次事件是联发科新聘先进封装副总裁在SEMICON Taiwan 2026论坛上的策略性发言，核心内容为'紧急强化先进封装能力并招募人才'。对联发科自身而言，这是超大市值主标的的软催化——无新增订单、无收入指引变化、无具体产品发布，仅是对既有AI ASIC战略方向的重复表述（448G SerDes、CoWoS/EMIB-T、CPO等均已在7月财报电话会披露）。对A股先进封装/OSAT公司而言，联发科建设内部封装能力不产生外包需求增量，CPO/硅光仍处早期研发无量产节点。对台积电而言，个别人才流动不影响其先进封装业务基本面。全链条无可交易的因果敞口。
📄 原文TrendForce↗ 原文
[News] MediaTek Ramps Up Advanced Packaging Push as TSMC Veteran Shang Hou Calls for More Talent
AI chip competition is expanding beyond advanced nodes into advanced packaging and silicon photonics. According to UDN…
不做 联发科（2454.TW）
超大市值主标的的软催化：新聘先进封装副总裁在行业论坛的策略性发言，无新增订单、收入指引或产品发布；AI ASIC先进封装布局（CoWoS/EMIB-T/448G SerDes/CPO）均已在7月财报电话会披露，本次无增量信息，不构成短线可交易催化
展开详情(成交明细 / 研究档案 / 原文全文 / 决策记录链)
研究档案
结论摘要
TrendForce报道联发科新任先进封装副总裁侯尚厚（前台积电CoWoS/硅光核心人物）在SEMICON Taiwan 2026发言称将紧急强化联发科先进封装能力。事件本质是人才战略宣示，非新增订单、收入或产品催化。联发科AI ASIC先进封装布局（CoWoS、EMIB-T、448G SerDes、CPO）均已在7月财报电话会披露，本次无增量信息。对超大市值主标的，软催化无金额增量不构成短线交易机会；对A股先进封装产业链，联发科自建能力不产生外包需求，映射缺乏因果支撑。结论：全链条无可交易标的。
🔎 新鲜度:最早出现 2026-08-31 · 扩散 low · price-in 风险 low ↗
先例如何影响了这次决策
对本次决策的影响:事件本身为软催化（人才+策略发言），无具体金额或订单变化，不构成需要历史先例校准的交易候选
方向:无可用先例
涨幅量级:无高相似先例可供校准
形态:无
工具执行结果 · 成功 2 · 降级 0 · 失败 0 · 取消 0
- search_processed_events 成功 stock_tools HTTP · 89 ms
{"result": "search_processed_events:agent query=`mediatek advanced packaging shang hou | mediatek ai asic cowos emib | semicon taiwan 2026 silicon photonics mediatek | 联发科 先进封装 人才`；结构化索引覆盖完整 72 小时；旧记录兼容扫描近 72.0/72 小时、1418 条本臂决策(完整)，返回 0 条候选。未命中只表示这些 agent query 表达式没有召回候选，不能据此证明消息首发或不是重复；按当前事件继续正常研判。 - fetch_decision_experience 成功 stock_tools HTTP · 594 ms
{
原文全文
展开原文 · 3,179 字
[News] MediaTek Ramps Up Advanced Packaging Push as TSMC Veteran Shang Hou Calls for More Talent
AI chip competition is expanding beyond advanced nodes into advanced packaging and silicon photonics. According to UDN News, MediaTek has been strengthening its capabilities in these areas, with Shang Hou, who recently joined the company as vice president of advanced packaging after retiring from TSMC, helping lead the effort. Appearing on August 31 at the SEMICON Taiwan 2026 Silicon Photonics International Forum, Hou said his first task at MediaTek is to “urgently strengthen” its advanced packaging capabilities and continue recruiting talent in the field.
Hou’s move has drawn significant industry attention. As the report highlights, he was deeply involved in TSMC’s advanced packaging and silicon photonics development and named the company’s COUPE (Compact Universal Photonic Engine) silicon photonics integration platform. He also worked on TSVs, chip stacking, and 2.5D CoWoS packaging, making him a key veteran of TSMC’s advanced packaging development.
The report notes that Hou’s move reflects MediaTek’s push to strengthen advanced packaging as it expands into AI data centers and large-scale ASICs. As AI chip competition shifts toward the joint optimization of logic chips, HBM, advanced packaging, and high-speed interconnects, technologies such as 2.5D and 3D packaging, CPO, and silicon photonics are requiring IC designers to consider packaging, thermal management, power delivery, and photonic-electronic integration earlier in the design process.
On the technology front, MoneyDJ notes that MediaTek said at its July earnings call that its 448G SerDes development is on track for completion in the second half of 2027. The company is using co-packaged copper (CPC) for high-speed, energy-efficient interconnects, while its next-generation solutions will move toward CPO, with development already underway on TSMC’s COUPE platform. MediaTek is also offering pre-validated subsystems spanning 3.5D platforms, memory, I/O, and high-speed interconnects to shorten time to market and expand its AI ASIC capabilities toward broader system and platform deployment.
MediaTek Deepens Advanced Packaging Push
Hou is not the only TSMC advanced packaging veteran to recently join MediaTek. As noted by TechNews, Douglas Yu, a key advanced packaging R&D veteran and one of TSMC’s so-called “Six R&D Knights,” joined MediaTek in May. Yu played a pivotal role in developing CoWoS and is expected to strengthen MediaTek’s integration of advanced packaging and chip design.
MediaTek is also diversifying its advanced packaging strategy. According to Commercial Times, the company disclosed during its latest earnings call that its AI ASIC projects are using both TSMC’s CoWoS and Intel’s EMIB-T advanced packaging technologies, signaling a more diversified approach to meet the varying requirements of customers developing large-scale AI chips.
Read more
- [News] Marvell, AMD Reportedly Shake Up Google TPU Race, Putting Broadcom, MediaTek Under Pressure
- [News] MediaTek Advances 400G SerDes on 2nm, Targeting Google TPU v10 and Meta AI ASIC Orders
(Photo credit: MediaTek)
AI chip competition is expanding beyond advanced nodes into advanced packaging and silicon photonics. According to UDN News, MediaTek has been strengthening its capabilities in these areas, with Shang Hou, who recently joined the company as vice president of advanced packaging after retiring from TSMC, helping lead the effort. Appearing on August 31 at the SEMICON Taiwan 2026 Silicon Photonics International Forum, Hou said his first task at MediaTek is to “urgently strengthen” its advanced packaging capabilities and continue recruiting talent in the field.
Hou’s move has drawn significant industry attention. As the report highlights, he was deeply involved in TSMC’s advanced packaging and silicon photonics development and named the company’s COUPE (Compact Universal Photonic Engine) silicon photonics integration platform. He also worked on TSVs, chip stacking, and 2.5D CoWoS packaging, making him a key veteran of TSMC’s advanced packaging development.
The report notes that Hou’s move reflects MediaTek’s push to strengthen advanced packaging as it expands into AI data centers and large-scale ASICs. As AI chip competition shifts toward the joint optimization of logic chips, HBM, advanced packaging, and high-speed interconnects, technologies such as 2.5D and 3D packaging, CPO, and silicon photonics are requiring IC designers to consider packaging, thermal management, power delivery, and photonic-electronic integration earlier in the design process.
On the technology front, MoneyDJ notes that MediaTek said at its July earnings call that its 448G SerDes development is on track for completion in the second half of 2027. The company is using co-packaged copper (CPC) for high-speed, energy-efficient interconnects, while its next-generation solutions will move toward CPO, with development already underway on TSMC’s COUPE platform. MediaTek is also offering pre-validated subsystems spanning 3.5D platforms, memory, I/O, and high-speed interconnects to shorten time to market and expand its AI ASIC capabilities toward broader system and platform deployment.
MediaTek Deepens Advanced Packaging Push
Hou is not the only TSMC advanced packaging veteran to recently join MediaTek. As noted by TechNews, Douglas Yu, a key advanced packaging R&D veteran and one of TSMC’s so-called “Six R&D Knights,” joined MediaTek in May. Yu played a pivotal role in developing CoWoS and is expected to strengthen MediaTek’s integration of advanced packaging and chip design.
MediaTek is also diversifying its advanced packaging strategy. According to Commercial Times, the company disclosed during its latest earnings call that its AI ASIC projects are using both TSMC’s CoWoS and Intel’s EMIB-T advanced packaging technologies, signaling a more diversified approach to meet the varying requirements of customers developing large-scale AI chips.
Read more
- [News] Marvell, AMD Reportedly Shake Up Google TPU Race, Putting Broadcom, MediaTek Under Pressure
- [News] MediaTek Advances 400G SerDes on 2nm, Targeting Google TPU v10 and Meta AI ASIC Orders
(Photo credit: MediaTek)
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