三星在 SEMICON Taiwan 2026 披露 HBM5、zHBM 与 zNAND-O 路线图

[News] Samsung Unveils Memory Roadmap at SEMICON: HBM5 Targets 2× HBM4E Performance, zHBM 8× Boost
Following Hot Chips 2026 in August, Samsung has revealed fresh details on its next-generation HBM and zHBM at SEMICON Taiwan 2026. On Sept. 1, Jangseok Choi, corporate vice president of Memory Product Planning at Samsung Electronics, said the company’s HBM5 is targeting 2× the performance and 20% higher performance per watt versus HBM4E, Newspim reports.
The performance gains will be paired with a 20% reduction in thermal resistance, helping HBM5 tackle the rising heat generated by increasingly powerful AI accelerators, the report notes.
Samsung is also taking HBM5 to a more advanced process, with the base die moving to its in-house 2nm node, from the 4nm process used for HBM4 and HBM4E, according to a June Tom’s Hardware report. On the other hand, per SeDaily, the memory giant is preparing 12-, 16- and 20-layer DRAM stacks for HBM5, with mass production expected around 2028, following HBM4E
zHBM Targets 8× HBM4E Performance
Looking beyond HBM, Samsung is also developing zHBM, targeting 8× the performance and 3× the performance per watt of HBM4E, Newspim reports, adding that the company also aims to reduce thermal resistance by 75%–90%.
According to Samsung, zHBM, which is a new architecture that differs from conventional HBM, stacks memory directly on top of the processor instead of placing memory beside the AI accelerator (xPU). By shortening the distance data must travel, the architecture delivers higher bandwidth and improved power efficiency. Hankyung notes that zHBM is expected to be launched after 2029.
zNAND-O Targets DRAM-Like Speed at NAND Scale
On the NAND front, Samsung is also developing next-generation memory technologies. News Tomato reports that zNAND-O, targeted for sampling in 2028, aims to deliver 10× the bit density of DRAM for large-scale data storage, while offering 7× the read bandwidth and power efficiency of NAND. The technology is designed to meet the growing AI demand for DRAM-like speed and NAND-like capacity, particularly from generative AI and large language models (LLMs).
Samsung’s CUBE Strategy Targets Four Memory Fronts
At the Memory Executive Summit held ahead of SEMICON Taiwan 2026, Samsung also outlined its “CUBE” framework for next-generation memory. According to TechNews, Choi said the strategy centers on four priorities: Capacity, Utilization, Bandwidth and Efficiency.
The report further explains that for capacity, Samsung plans to expand memory vertically to increase capacity without enlarging the printed circuit board (PCB) footprint. On utilization, the company sees 3D memory as more than simply stacking layers, instead optimizing the architecture and the placement of logic and memory to reduce latency.
For bandwidth, Samsung aims to shorten die-to-die distances by replacing horizontal data paths with vertical high-speed channels, TechNews notes. On efficiency, the focus is on power consumption and thermal management, minimizing the energy required to move each bit of data and maximizing performance per watt.
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