AMD MI455X采用TSMC 2nm与CoWoS-L，带动先进封装需求预期升温

[News] AMD Unveils MI455X Targeting Nvidia Rubin; TSMC 2nm, CoWoS-L Demand Seen Rising
AMD unveils its sixth-generation EPYC 9006 server CPU and Instinct MI455X GPU, expanding its AI portfolio across agentic AI, cloud computing, enterprise, and high-performance computing (HPC). According to Commercial Times , the move is expected to drive demand for TSMC’s advanced packaging technologies, including CoWoS-L and SoIC. Meanwhile, AMD notes that the EPYC Venice processor has entered volume production on TSMC’s advanced 2nm process technology, while the MI455X is built using TSMC 2nm and 3nm FinFET technologies.

Advanced Packaging Across AMD’s Chip Portfolio

Advanced packaging is becoming a key differentiator across AMD’s AI product roadmap. As Tom’s Hardware notes, the MI455X integrates 320 billion transistors using multiple advanced packaging technologies. Four Accelerator Complex Dies (XCDs) are hybrid-bonded onto each Fabric and Cache Die (FCD), while the two FCDs are interconnected with 12 HBM4 stacks, two I/O dies, and each other using TSMC’s CoWoS-L packaging technology.

The technology is also expected to extend to AMD’s next-generation CPUs. According to the Commercial Times, some high-end EPYC Venice models are reportedly expected to adopt TSMC’s CoWoS-L packaging and be manufactured at TSMC’s Kaohsiung Fab 22, with production expected to ramp in the second half of 2026 to support growing demand for agentic AI servers.

Commercial Times adds that CoWoS-L capacity remains tight. Sources cited by the report say some Chip-on-Wafer (CoW) orders are expected to be outsourced to ASE, while TSMC and OSAT providers continue expanding CoWoS capacity with visibility extending through 2027 and 2028. Depending on customer demand, TSMC may also source silicon interposers from UMC and Vanguard, further expanding the role of mature-node foundries in AI advanced packaging.

Looking further ahead, Commercial Times says AMD’s MI450, MI455X, and future AI chips are expected to boost SoIC (System-on-Integrated-Chips) demand. Institutional investors cited by the report estimate that TSMC’s SoIC capacity will reach 15,000–20,000 wafers per month by the end of 2026, before doubling again by the end of 2027. Separately, Commercial Times also notes that AMD’s Zen 7 processors, expected to launch next year, could adopt Powertech’s FOPLP (Fan-Out Panel-Level Packaging), with trial production expected in the second half of 2026 and potential mass production as early as 2027.

Head-to-Head with Nvidia Rubin

Compared with Nvidia’s Rubin, the MI455X introduces several key differences in memory and compute performance. According to Wccftech , AMD’s Instinct MI455X adopts HBM4 memory, increasing capacity by 50% from 288GB of HBM3E on the MI350 series to 432GB. Memory bandwidth also rises to 22.3 TB/s, up 2.8× from 8 TB/s on its predecessor.

By comparison, Nvidia’s Rubin GPU is equipped with 288GB of HBM4 memory and delivers up to 22 TB/s of bandwidth. On compute performance,  Wccftech reports that the MI455X delivers up to 40 PFLOPs of FP4 and 20 PFLOPs of FP8 performance—roughly doubling the compute capability of the MI350 series. By comparison, Nvidia’s Rubin GPU provides 50 PFLOPs of FP4 and 17.5 PFLOPs of FP8 performance.

Customer commitments are also taking shape. The Commercial Times reports that partner Anthropic has committed to invest US$5 billion and will deploy data centers powered by the latest Instinct MI450-series GPUs, with the first 1 GW phase expected to come online in the first half of 2027.

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(Photo credit: AMD)

Please note that this article cites information from  AMD ,  Commercial Times ,  Tom’s Hardware , and  Wccftech .